DA9021 datasheet(53/142 Pages) DIALOG

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DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

53 of 142

12.3 2-wire communication

The power manager interface can be configured for a 2-wire serial data exchange. It has a

configurable SLAVE write address (default: 0x90) and a configurable SLAVE read address (default:

0x91).

SK provides the 2-wire clock and SO carries all the power manager bidirectional 2-wire data. The 2-

wire interface is open-drain supporting multiple devices on a single line. The bus lines have to be

pulled HIGH by external pull-up resistors (2 k

Ω to 20 kΩ range). The attached devices only drive the

bus lines LOW by connecting them to ground. As a result two devices cannot conflict, if they drive the

bus simultaneously. In standard/fast mode the highest frequency of the bus is 400 kHz. The exact

frequency can be determined by the application and does not have any relation to the DA9021/22

internal clock signals. DA9021/22 will follow the host clock speed within the described limitations and

does not initiate any clock arbitration or slow down.

In high speed mode the maximum frequency of the bus can be increased up to 1.7 MHz. This mode

is supported if the SK line is driven with a push-pull stage from the host and if the host enables an

external 3 mA pull-up at the SO pin to decrease the rise time of the data. In this mode the SO line on

DA9021/22 is able to sink up to 12 mA. In all other respects the high speed mode behaves as the

standard/fast mode.

Communication on the 2-wire bus always takes place between two devices, one acting as the master

and the other as the slave. The DA9021/22 will only operate as a slave. As opposed to the 4-wire

mode the 2-wire interface has direct (linear) access to the whole DA9021/22 register space (except

R0/R128). This is achieved by using the MSB of the 2-wire, 8-bit register address as a selector of the

mode).

12.3.1

2-wire control bus protocol

All data is transmitted across the 2-wire bus in groups of 8 bits. To send a bit the SO line is driven

towards the independent state while the SK is LOW (a low on SO indicates a zero bit). Once the SO

has settled the SK line is brought HIGH and then LOW. This pulse on SK clocks the SO bit into the

receivers shift register.

A two byte serial protocol is used containing one byte for address and one byte for data. Data and

address transfer is MSB transmitted first for both read and write operations. All transmission begins

with the START condition from the master during the bus is in IDLE state (the bus is free). It is

initiated by a high to low transition on the SO line while the SK is in the HIGH state (a STOP

condition is indicated by a low to high transition on the SO line while the SK is in the HIGH state).

The 2-wire bus will be monitored by DA9021/22 for a valid SLAVE address whenever the interface is

enabled. It responds immediately when it receives its own slave address. These acknowledge is

done by pulling the SO line low during the following clock cycle (white blocks marked with

“A” in

Figure 29 to Figure 33).

The protocol for a register write from master to slave consists of a start condition, a slave address

with read/write bit and the 8-bit register address followed by 8 bits of data terminated by a STOP

condition (all bytes responded by DA9021/22 with Acknowledge):

SK/

SLK

SO/

DATA

Figure 29: Timing of 2-wire START and STOP condition

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