DA9021 datasheet(49/142 Pages) DIALOG

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DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

49 of 142

12 Control interfaces

The DA9021/22 is completely software controlled from the host by registers. DA9021/22 offers two

independent serial control interfaces to access these registers. The communication via the main

power manager interface is selectable to be either a 2-wire or a 4-wire connection (I

2C or SPI

compliant). The alternate interface is fixed towards a 2-wire bus. Data is shifted in to or out from

DA9021/22 under the control of the host processor that also provides the serial clock.

12.1 Power manager interface (4-wire and 2-wire control bus)

This is the dedicated power control interface from the primary host processor. In 4-wire mode the

interface uses a chip-select line (nCS/nSS), a clock line (SK), data input (SI) and data output line

(SO).

12.2 4-wire communication

In 4-wire mode the DA9021/22 register map is split into two pages with each page containing up to

128 registers. The register at address zero on each page is used as a page control register. The

default active page after reset includes registers R1 to R127. Writing to the page control register

changes the active page for all subsequent read/write operations. After modifying the active page it is

recommended to read back the page control register to ensure that future data exchange is

accessing the intended registers.

The 4-wire interface features a half-duplex operation (data can be transmitted and received within a

single 16-bit frame) at enhanced clock speed (up to 14 MHz). It operates at the provided host clock

frequencies.

DA9021

(slave)

Host

processor

nCS/nSS

VDDIO

Slave device

nCS/nSS

VDDIO

4-WIRE interface

Host

processor

DA9021

Peripheral

device

Peripheral

device

SDA

SCL

SDA

VDDIO

2-WIRE interface

Figure 24: Schematic of 4-wire and 2-wire power manager bus

A transmission begins when initiated by the host. Reading and writing is accomplished by the use of

an 8-bit command, which is sent by the host prior to the exchanged 8-bit data. The byte from the host

begins shifting in on the SI pin under the control of the serial clock SK provided from the host. The

first 7 bits specify the register address (0 to 127, decimal) which will be written or read by the host.

The register address is automatically decoded after receiving the seventh address bit. The command

word ends with an R/W bit, which specifies the direction of the following data exchange.

During register writing the host continues sending out data during the following 8 SK clocks. For

reading the host stops transmitting and the 8-bit register is clocked out of DA9021/22 during the

consecutive eight SK clocks of the frame. Address and data are transmitted with MSB first. nCS

resets the interface when inactive and it has to be released between successive cycles.

The SO output from DA9021/22 is normally in high-impedance state and active only during the

second half of read cycles. A pull-up or pull-down resistor may be needed at the SO line if a floating

logic signal is causing unintended current consumption inside other circuits.

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