AD9671EBZ datasheet(47/61 Pages) AD

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AD9675

Data Sheet

Rev. A | Page 46 of 60

Table 30. AD9675 SPI Write Start-Up Sequence Example

Address

Value

Description

0x000

0x3C

Initiate SPI reset

0x002

0x0X (default)

Set speed mode to 40 MSPS

0x0FF

0x01

Enable speed mode change

0x004

0x0F

Set local registers to all channels

0x005

0x3F

Set local registers to all channels

0x113

0x00

Bypass RF decimator, enable high-pass filter

0x011

0x06 (default)

Set LNA gain= 21.6 dB, GAIN± pins enabled, and PGA gain = 24 dB

0xF00

0xFF

Continuous run mode enable; do not power down channels (POWER_STOP LSB)

0xF01

0x7F

Continuous run mode enable; do not power down channels (POWER_STOP MSB)

0xF02

0x00

Power up all channels 0 clock cycles after TX_TRIG± signal assertion (POWER_START LSB)

0xF03

0x80

Digital high-pass bypassed (POWER_START MSB)

0x10C1

0x00 (default)

Set index profile (required after profile memory writes)

0x014

0x00

Set output data format

0x008

0x00

Chip run (TGC mode)2

0x021

0x12

16-bit, four-lane mode

0x199

0x80

Enables automatic serializer/deserializer (SERDES) sample clock counter

0x142

0x04

ILAS enabled

0x188

0x01

Enable start code identifier

0x18B

0x27

Set start code MSB

0x18C

0x72

Set start code LSB

0x150

0x03

JESD204B scrambler disabled and four-lane configuration (L = 4)

0x182

0x82

Automatically configures PLL

0x181

0x02

PLL N-divider = ÷20

0x186

0xAA

Disable continuous data resync (continuous data resync is not recommended during real-time

scanning; one time data resync is sufficient)

0x10C3

0x20

Set SPI TX_TRIG± and index profile

0x00F

0x18

Set low-pass filter cutoff frequency, bandwidth mode

0x02B

0x40

Set analog LPF and HPF to defaults, tune filters4

1 Setting the profile index requires an additional SPI write in SPI MSB mode before the chip is run to complete the current profile buffer update.

2 Running the chip from full power-down mode requires 375 μs wake up time as listed in Table 3.

3 Soft TX_TRIG switches the RF decimator and filter to a running state. The soft TX_TRIG may not be needed if a hardware TX_TRIG signal is used to run the digital block.

4 Tuning the filters requires 512 ADC clock cycles.

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