AD9671EBZ datasheet(30/61 Pages) AD

30 / 61 page

Data Sheet

AD9675

Rev. A | Page 29 of 60

digital, and clock sections of the PCB, optimum performance

can be easily achieved.

Advanced Power Control

For an ultrasound system, not all channels are needed during all

scanning periods. The POWER_START and POWER_STOP

values in the vector profile can be used to delay the channel

startup and turn the channel off after a certain number of samples.

These counters are relative to TX_TRIG±. The analog circuitry

needs to power up before the digital one and the advance time

(POWER_SETUP) for powering up the analog circuitry, before

POWER_START, is set up in Address 0x112 (see Table 31).

Figure 44. Power Sequencing

DIGITAL OUTPUTS AND TIMING

JESD204B Transmit Top Level Description

The AD9675 digital output complies with the JEDEC Standard

JESD204B, Serial Interface for Data Converters. JESD204B is a

protocol to link the AD9675 to a digital processing device over

a serial interface up to 5 Gbps link speeds. The benefits of the

JESD204B interface include a reduction in required board area

for data interface routing, and enables smaller packages for

converter and logic devices. The AD9675 supports single, dual,

or quad lane interfaces.

JESD204B Overview

The JESD204B data transmit block, as shown in Figure 45,

assembles the parallel channel data from the ADC or digital

processing block into frames and uses 8-bit/10-bit encoding as

well as optional scrambling to form serial output data. Lane

synchronization is supported through the use of special

characters during the initial establishment of the link, and

additional synchronization is embedded in the data stream

thereafter. A matching external receiver is required to lock onto

the serial data stream and recover the data and clock. For

additional details on the JESD204B interface, users are

encouraged to refer to the JESD204B standard.

The AD9675 JESD204B transmit block maps the eight channel

outputs over a link. A link can be configured to use either single,

dual, or quad serial differential outputs, which are called lanes.

The JESD204B specification refers to a number of parameters to

define the link, and these parameters must match between the

JESD204B transmitter (AD9675 output) and receiver.

The JESD204B link is described according to the parameters

listed in Table 14.

Table 14. JESD204B Parameters

Parameter

Description

AD9675 Value

Samples transmitted per single converter per frame cycle

Number of converters per converter device

Number of lanes per converter device

1, 2, or 4

Converter resolution

12, 14, or 16

Total number of bits per sample

Number of control words per frame clock cycle per

converter device

Number of control bits per conversion sample

Number of frames per multiframe

Configurable on the AD9675

High density mode

Octets per frame

4, 8, 16, or 32 (dependent on L = 4, 2, or 1, respectively)

Control bit

Tail bit

Available on the AD9675

SCR

Scrambler enable/disable

Configurable on the AD9675

FCHK

Checksum for the JESD204B parameters

Automatically calculated and stored in the register map

TX_TRIG±

POWER_STOP

(PROFILE SPECIFIC)

POWER_START

(PROFILE SPECIFIC)

POWER_SETUP

(SPI SET)

DIGITAL

POWER

ANALOG

POWER

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