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AD9675

Data Sheet

Rev. A | Page 40 of 60

DIGITAL RF DECIMATOR

The AD9675 contains digital processing capability. Each channel

has two stages of processing that are available: RF decimator and

high-pass filter. For test purposes, the input to the decimator can

serve as a test waveform. Normally, the input is the output of the

ADC. The output of the decimator/filter is sent to the framer/

serializer for output formatting.

The maximum data rate of the framer/serializer is 65 MSPS.

Therefore, if the sample of the ADC is greater than 65 MSPS,

enable the RF decimator (fixed rate of 2). The ADC resolution

is 14 bits. Saturation of the ADC is determined after the dc offset

calibration to ensure maximum dynamic range.

VECTOR PROFILE

To minimize the time needed to reconfigure device settings

during operation, the device supports configuration profiles.

The user can store up to 32 profiles in the device. A profile is

selected by a 5-bit index. A profile consists of a 64-bit vector,

as described in Table 27. Each parameter is concatenated to

form the 64-bit profile vector. The profile memory starts at

in either stream or address selected data mode. However, the

user must read the memory using stream mode. When writing

or reading in stream mode while the SPI configuration is set to

MSB first mode (default setting for register 0x000) then the

write/read address needs to refer to the last register address, not

the first one. For example, writing or reading the first profile

that spans the address space between 0xF00 and 0xF07, and the

SPI port is configured as MSB first, then the referenced address

must be 0xF07 to allow reading or writing the profile 64 bits in

MSB mode. For more information about stream mode, see the

AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

There is a buffer used to store the current profile data. When

the profile index is written in Register 0x10C, the selected

profile is read from memory and stored in the current profile

buffer. The profile memory is read/written in the SPI clock

domain. Once the SPI writes the profile index value, it takes

four SPI clock cycles to read the profile from RAM and store it

in the current profile buffer. If the SPI is in LSB mode, these

additional SPI clock cycles are provided when the profile index

needs to be read or written to update the profile buffer.

Updating profile memory does not affect the data in the profile

buffer. The profile index register must be written to cause a

refresh of the current profile data, even if the profile index

Figure 56. Simplified Block Diagram of a Single Channel of RF Decimator

Table 27. Profile Definition

Field

No. of Bits

Description

Reserved

HPF Bypass

Digital high-pass filter bypass

0 = disable (filter enabled)

1 = enable (filter bypassed)

POWER_START

ADC clock cycles counted from the TX_TRIG signal assertion when the active channels are powered up

0x0000 = 0 clock cycles

0x0001 = 1 clock cycle

…

0x7FFF = 32,767 clock cycles

Reserved

POWER_STOP

ADC clock cycles counted from the TX_TRIG signal assertion when the active channels are powered down

0x0000 = 0 clock cycles

0x0001 = 1 clock cycle

…

0x7FFF = continuous run mode

ADC OUTPUT OR

TEST WAVEFORM

DC OFFSET

CALIBRATION

RF DECIMATOR

MULTIBAND AAF

DECIMATE BY 2

FRAMER

SERIALIZER

HIGH-PASS

FILTER

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