AD5593R datasheet(24/34 Pages) AD

24 / 34 page

Data Sheet

AD5593R

Rev. C | Page 23 of 33

START BY

MASTER

ACK. BY

AD5593R

ACK. BY

AD5593R

SCL

(CONTINUED)

SDA

(CONTINUED)

SCL

(CONTINUED)

SDA

(CONTINUED)

SCL

(CONTINUED)

SDA

(CONTINUED)

FRAME 2

POINTER BYTE

FRAME 1

SLAVE ADDRESS

SCL

SDA

FRAME 3

LEAST SIGNIFICANT

DATA BYTE

D15

D14

D13

D12

D11

D10

FRAME 4

MOST SIGNIFICANT

DATA BYTE

FRAME 2

MOST SIGNIFICANT

DATA BYTE

FRAME 1

SLAVE ADDRESS

REPEAT START

BY MASTER

ACK. BY

AD5593R

ACK. BY

MASTER

ACK. BY

MASTER

ACK. BY

MASTER

D15

D14

D13

D12

D11

D10

ACK. BY

MASTER

FRAME 5

LEAST SIGNIFICANT

DATA BYTE

STOP BY

MASTER

1ONLY APPLICABLE IF AN ADC SEQUENCE HAS BEEN SELECTED.

START OF ADC

CONVERSION1

Figure 37. I2C Block Read

POINTER BYTE

The pointer byte contains eight bits. Bits[D7:D4] are mode bits

that select the operation to be executed. The data contained in

Bits[D3:D0] depend on the operation required. Table 9 shows

the configuration of the pointer byte. When Bits[D7:D4] are

0b0000, the mode dependent bits (Bits[D3:D0]) select a control

contained in the MSB and LSB as shown in Figure 34. The mode

dependent data bits also select which DAC is updated during a

DAC write operation and which register is selected for readback.

Table 9. Pointer Byte Configuration

Mode bits

Mode dependent data bits

Table 10. Mode Bits

Description

Configuration mode

DAC write

ADC readback

DAC readback

GPIO readback

CONTROL REGISTERS

Table 11 shows the control register map for the AD5593R. The

control registers configure the I/O pins and set various

operating parameters in the AD5593R, such as enabling the

reference, selecting the LDAC mode function, or selecting

power-down modes. The control registers are written to using

the 4-byte I2C write sequence shown in Figure 34. To write to a

control register, the mode bits (Bits[D7:D4]) of the pointer byte

are zeros. The mode dependent data bits (Bits[D3:D0]) of the

pointer byte select which control register is to be accessed. The

data to be written to the control register is contained in the

most significant and least significant data bytes. These contain a

total of 16 bits and are shown as D15 to D0 in Table 12 and

Table 13. The contents of the control registers can be read back

using the read sequence shown in Figure 35 or Figure 36.

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