AD5593R datasheet(22/34 Pages) AD

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Data Sheet

AD5593R

Rev. C | Page 21 of 33

SERIAL INTERFACE

The AD5593R has a 2-wire, I2C-compatible serial interface

(refer to The I2C -Bus Specification, Version 2.1, January 2000).

The AD5593R is connected to an I2C bus as a slave device

under the control of a master device. See Figure 2 for a timing

diagram of a typical write sequence. The AD5593R supports

standard mode (100 kHz) and fast mode (400 kHz). Support is

not provided for 10-bit addressing and general call addressing.

The AD5593R has a 7-bit slave address; its six MSBs are set to

001000. The LSB is set by the state of the A0 address pin, which

determines the state of the A0 bit. The facility to change the

logic level of the A0 pin before a read or write operation allows

the user to incorporate multiple AD5593R devices on one bus.

The 2-wire serial bus protocol operates as follows: the master

initiates data transfer by establishing a start condition when a

high-to-low transition on the SDA line occurs while SCL is

high. The following byte is the address byte, which consists of

the 7-bit slave address. The slave address corresponding to the

transmitted address responds by pulling SDA low during the

ninth clock pulse (this is termed the acknowledge bit). At this

stage, all other devices on the bus remain idle while the selected

device waits for data to be written to or read from its shift register.

Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

The transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of SCL.

When all data bits have been read or written, a stop condition is

established.

In write mode, the master pulls the SDA line high during the

10th clock pulse to establish a stop condition. In read mode, the

master issues a no acknowledge for the ninth clock pulse (that

is, the SDA line remains high). The master brings the SDA line

low before the 10th clock pulse and then high during the 10th

clock pulse to establish a stop condition.

WRITE OPERATION

When writing to the AD5593R, the user must begin with a start

command followed by an address byte R/W = 0), after which

the AD5593R acknowledges that it is prepared to receive data

by pulling SDA low. The AD5593R requires three bytes of data.

The first byte is the pointer byte. This byte contains information

defining the type of operation that is required of the AD5593R,

such as configuring the I/O pins and writing to a DAC. The pointer

byte is followed by the most significant byte and the least

significant byte, as shown in Figure 34. After these data bytes

are acknowledged by the AD5593R, a stop condition follows.

READ OPERATION

When reading data back from the AD5593R, the user begins

with a start command followed by an address byte (R/W = 0),

after which the DAC acknowledges that it is prepared to transmit

data by pulling SDA low. The pointer byte is then written to select

what is to be read back. A repeat start or a new I2C transmission

can then follow to read two bytes of data from the AD5593R.

Both bytes are acknowledged by the master, as shown in Figure 35.

It is also possible to perform consecutive readbacks without

having to provide interim start and stop conditions or slave

addresses. This method can be used to read blocks of

conversions from the ADC, as shown in Figure 37.

FRAME 2

POINTER BYTE

FRAME 1

SLAVE ADDRESS

SCL

START BY

MASTER

ACK. BY

AD5593R

ACK. BY

AD5593R

ACK. BY

AD5593R

ACK. BY

AD5593R

SDA

R/W

FRAME 4

LEAST SIGNIFICANT

DATA BYTE

FRAME 3

MOST SIGNIFICANT

DATA BYTE

STOP BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Figure 34. 4-Byte I2C Write

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