AD5593R datasheet(20/34 Pages) AD

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Data Sheet

AD5593R

Rev. C | Page 19 of 33

Calculating ADC Input Current

The current flowing into the I/Ox pins configured as ADC inputs

varies with sampling rate (fS), the voltage difference between

successive channels (VDIFF), and whether buffered or unbuffered

mode is used. Figure 33 shows a simplified version of the ADC

input structure. When a new channel is selected for conversion,

5.8 pF must be charged to or discharged from the voltage that

on the previously selected channel. The time required for the

charge or discharge depends on the voltage difference between

the two channels. This dependence affects the input impedance

of the multiplexer and, therefore, the input current flowing into

the I/Ox pins.

In buffered mode, Switch S1 is open and Switch S2 is closed. In

buffered mode, the U1 buffer directly drives the 23.1 pF capacitor

and the charging time of the capacitors is negligible. In unbuffered

mode, Switch S1 is closed and Switch S2 is closed. In unbuffered

mode, the 23.1 pF capacitor must be charged from the I/Ox

pins; this charging contributes to the input current. For

applications where the ADC input current is too high, an external

input buffer may be required. The choice of buffer is a function

of the particular application.

Calculate the input current for buffered mode as follows:

fS × C × VDIFF + 1 nA

where:

fS is the ADC sample rate in Hz.

C is the sampling capacitance in farads.

VDIFF is the voltage change between successive channels.

Calculate the input current for buffered mode as follows:

fS × C × VDIFF

where 1 nA is the dc leakage current associated with unbuffered

mode.

The input current for the ADC in buffered mode, where

I/O0 = 0.5 V, I/O1 = 2 V, and fS = 10 kHz, is as follows:

(10,000 × 5.8 × 10−12 × 1.5) + 1 nA = 88 nA

Under the same conditions, the ADC input current in unbuffered

mode is as follows:

(10,000 × 28.9 × 10−12 × 1.5) = 433.5 nA

5.8pF

I/O0

I/O7

COMPARATOR

CONTROL

LOGIC

23.1pF

300

Figure 33. ADC Input Structure

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