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AD5593R

Data Sheet

Rev. C | Page 6 of 33

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = 2.7 V to

5.5 V, 1.8 V ≤ VLOGIC ≤ VDD; 2.5 V ≤ VREF≤ VDD; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1

Min

Typ

Max

Unit

Conditions/Comments

2.5

µs

SCL cycle time

0.6

µs

tHIGH, SCL high time

1.3

µs

tLOW, SCL low time

0.6

µs

tHD,STA, start/repeated start condition hold time

100

tSU,DAT, data setup time

t62

0.9

µs

tHD,DAT, data hold time

0.6

µs

tSU,STA, setup time for repeated start

0.6

µs

tSU,STO, stop condition setup time

1.3

µs

tBUF, bus free time between a stop and a start condition

t10

300

tR, rise time of SCL and SDA when receiving

tR, rise time of SCL and SDA when receiving (CMOS compatible)

t11

250

tF, fall time of SDA when transmitting

tF, fall time of SDA when receiving (CMOS compatible)

300

tF, fall time of SCL and SDA when receiving

20 + 0.1CB3

tF, fall time of SCL and SDA when transmitting

CB3

400

Capacitive load for each bus line

Guaranteed by design and characterization; not production tested.

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling

edge of SCL.

CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.

Timing Diagram

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

SDA

SCL

t10

t11

Figure 2. 2-Wire Serial Interface Timing Diagram

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