ADATE320 datasheet(21/83 Pages) AD

21 / 83 page

ADATE320

Data Sheet

Rev. B | Page 20 of 82

Parameter

Min

Typ

Max

Unit

Test

Level

Test Conditions/Comments

ALARM Output Characteristics

Off State Leakage

500

Disable alarm, apply VDD to ALARM pin, and

measure leakage current

Maximum On Voltage at 200 µA

0.1

0.7

ALARM pin asserted, force 200 µA into pin and

measure voltage

AC SPECIFICATIONS

Propagation Delay

0.5

µs

For OVDH: VDUTx = 0.0 V to 4.5 V step, OVDH = 4.0 V,

OVDL = −1.0 V; for OVDL: VDUTx = 0.0 V to −1.5 V step,

OVDH = 4.0 V, OVDL = −1.0 V

SERIAL PROGRAMMABLE INTERFACE (SPI) SPECIFICATIONS

Table 13.

Parameter

Min

Typ

Max

Unit

Test

Level

Test Conditions/Comments

DC SPECIFICATIONS

Input Voltage

RST, CS, SCLK, SDI

Logic High

VDD − 0.7

VDD

Logic Low

0.0

0.7

Input Bias Current

−10

+10

µA

Tested at 0.0 V and VDD; RST tested at VDD; RST has an internal

50 kΩ pull-up to VDD

SCLK Crosstalk on DUTx Pin

DCL disabled, PPMU forcing 0.0 V

Serial Output

Logic High

VDD − 0.5

VDD

SDO, sourcing 2 mA

Logic Low

0.0

0.5

Sinking 2 mA

BUSY Output Characteristics

Open-drain output

Off State Leakage

500

BUSY pin not asserted, apply VDD to pin and measure

leakage current

Maximum OnVoltage at 2 mA

0.01

0.7

BUSY pin asserted, force 2 mA into pin and measure voltage

SPI TIMING SPECIFICATIONS

Table 14.

Parameter

Symbol

Min

Typ

Max

Unit

Test

Level

Description

SCLK Operating Frequency

fCLK

MHz

0.5

100

MHz

SCLK High Time

tCH

4.5

SCLK Low Time

tCL

4.5

CS to SCLK Setup at Assert

tCSAS

1.5

Setup time of CS assert to next rising edge of SCLK.

CS to SCLK Hold at Assert

tCSAH

1.5

Hold time of CS assert to next rising edge of SCLK.

CS to SCLK Setup at

Release

tCSRS

1.5

Setup time of CS release to next rising edge of SCLK.

CS to SCLK Hold at Release

tCSRH

1.5

Hold time of CS release to next rising edge of SCLK. This parameter

is only critical if the number of SCLK cycles from previous release of

CS is the minimum specified by the tCSAM parameter.

CS Assert to SDO Active

tCSO

Delay time from CS assert to SDO active state.

CS Release to SDO High-Z

tCSZ

Delay from CS release to SDO high-Z state, strongly influenced

by external SDO pin loading.

CS Release to Next Assert

tCSAM

Cycles

Minimum release time of CS between consecutive assertions of

CS. This parameter is specified in units of SCLK cycles, more

specifically in terms of rising edges of the SCLK input.

ADATE320 датащи(PDF) 21 Page - Analog Devices

ADATE320 датащи(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

датащи скачать

ссылки URL