ADATE320 datasheet(52/83 Pages) AD

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Data Sheet

ADATE320

Rev. B | Page 51 of 82

SPI Clock Cycles and the BUSY Pin

The ADATE320 offers a digital BUSY output pin to indicate that

the SPI controller requires more SCLK cycles to be input on the

SCLK pin. The device may be operated without this pin, but care

must be exercised to ensure that the required number of SCLK

cycles are provided in each case to complete each SPI instruction.

After any valid SPI instruction is written to the ADATE320, the

BUSY pin is asserted to indicate a busy status of the DAC update

and calibration routines. The BUSY pin is an open-drain output

capable of sinking a minimum of 2 mA from the VDD supply. It

is recommended to tie the BUSY pin to VDD with an external 1 kΩ

pull-up resistor.

It is not a requirement to wait for release of BUSY prior to a

subsequent assertion of the CS pin. As long as the minimum

number of SCLK cycles following the previous release of CS is

met according to the tCSAM parameter, the CS pin can again be

asserted for another SPI operation. With the one exception of

recovery from a reset request (either by hardware assertion of

RST pin or software setting of the internal SPI_RESET control bit),

there is no scenario in normal operation of the ADATE320 in

which the user must wait for release of BUSY before asserting

the CS pin for a subsequent SPI operation. The only requirement

on the assertion of CS is that the tCSAM parameter has been met

as defined in Figure 2 and Table 14.

It is very important, however, that the SCLK pin continue to

operate for as long as the BUSY pin state remains active. This

period of time is defined by the parameter tBUSW and is defined in

Figure 2, Table 14, and Table 23. If the SCLK pin does not remain

active for at least the number of cycles specified, operations

pending to the internal processor may not fully complete. In

such a case, a temporary malfunction of the ADATE320 may

occur, or unexpected results may be obtained. After the device

releases the BUSY pin (or the required minimum number of clock

cycles is satisfied), SCLK may again be stopped to prevent any

unwanted digital noise from coupling into the analog functions.

In every case (with no exception for reset recovery), it is the

purpose of the BUSY pin to notify the supervisory ASIC or FGPA

that it is again safe to stop the SCLK signal. Running SCLK for

extra periods when BUSY is not active is never a problem except

for the possibility of adding unwanted digital switching noise

into analog functions.

The required length of the BUSY period (tBUSW) is variable

depending on the particular preceding SPI instruction, but it is

always deterministic. It depends only on factors such as whether

the previous instruction involved a write to one or more DAC

addresses, and, if so, how many channels were involved and

whether calibration was enabled. Table 23 details the length of

the tBUSW requirement in units of rising edge SCLK cycles for

each possible SPI instruction scenario, including recovery from

a hardware RST reset.

Because tBUSW is deterministic, it is therefore possible to predict

in advance the minimum number of rising edge SCLK cycles

that are required to complete any given SPI instruction, which

makes it possible to operate the device without a need to monitor

the BUSY pin. For applications in which it is neither possible

nor desirable to monitor the pin, it is acceptable to use the

deterministic information provided in Table 23 to guarantee the

minimum number of cycles is provided. Either way, it is necessary

to honor the minimum number of required rising edge SCLK

cycles, as defined by tBUSW, following the release of CS for each

of the SPI instruction scenarios listed.

Table 23. BUSY Minimum SCLK Cycle Requirements

SPI Instruction Type (Single- or Dual-Channel Operation)

Minimum tBUSW (SCLK Cycles)

Following Release of Asynchronous RST Reset Pin (Hardware Reset)

744

Following Assertion of the SPI_RESET Control Bit (Software Reset)

744

Write to No Operation (NOP) (Address 0x00, Address 0x20, Address 0x50, Address 0x60)

Write to a Valid Address That Is Not a DAC (Address > 0x10)

Write to Any DAC Except VILx or VIHx (Address 0x01 to Address 0x0F, Except Address 0x01 and

Address 0x03)

Write to VILx or VIHx DAC (Address 0x01 or Address 0x03)

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