AD5560JSVUZ datasheet(43/67 Pages) AD

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AD5560

Data Sheet

Rev. E | Page 42 of 66

Force the voltage on FORCE via SYS_FORCE and

measure the voltage at MEASOUT. The

difference is the error between the actual forced

voltage and the voltage at MEASOUT.

Calibrate the measure current (two-point calibration).

In FV mode, write zero scale to the FIN DAC registers

(Register 0x8 to Register 0xA).

Disconnect the FORCE pin and the SENSE pin.

Connect SYS_FORCE to FORCE (via SW8) and

SYS_SENSE to SENSE (via SW9).

Connect the SYS_FORCE pin to an external ammeter

and its other terminal to the SYS_SENSE pin.

Connect the SYS_SENSE pin to a precision resistor

(RDUT), where RDUT = RSENSE × 20 of the current range,

and connect its other terminal to ground (see Figure 58).

Measure the error between the ammeter reading and

the MEASOUT reading by forcing ±10 V to the FIN

DAC registers (Register 0x8 to Register 0xA).

Repeat Step 3a through Step3e across all current

ranges.

Similarly, calibrate the comparator and clamp DACs, and

load the appropriate gain and offset registers. Calibrating

these DACs requires some successive approximation to

determine where the comparator trips or the clamps

engage.

RSENSE

FIN

DAC

ISENSE

VSENSE

SYS_SENSE

SW9

SYS_FORCE

SENSE

FORCE

SW8

MEASOUT

EXTERNAL

AMMETER

RDUT

WHERE:

RDUT = RSENSE × 20

AD5560

Figure 58. Measure Current Calibration

CHOOSING AVDD/AVSS POWER SUPPLY RAILS

As noted in the Specifications section, the minimum supply

variation across the part is |AVDD − AVSS| ≥ 16 V and ≤ 33 V,

AVDD ≥ 8 V, and AVSS ≤ −5 V. For the AD5560 circuits to

operate correctly, the supply rails must take into account not

only the force voltage range but also the internal DAC

minimum voltage level, as well as headroom/footroom.

The DAC amplifier gains VREF by 5.125, and the offset DAC

centers that range about some chosen point. Because the DAC

minimum voltage (VMIN) is used in other parts of the circuit

(MEASOUT gain of 0.2), it is important that AVSS be chosen

based on the following:

AVSS ≤ −5.125 × (VREF × (OFFSET_DAC_CODE/216)) −

AVSS_Headroom − VDUTGND − (RCABLE × ILOAD)

where:

AVSS_Headroom is the 2.75 V headroom (includes the RSENSE

voltage drop).

VDUTGND is the voltage range anticipated at DUTGND.

RCABLE is the cable/path resistance.

ILOAD is the maximum load current.

When choosing AVDD, remember to take into account the

specified current ranges. The measure current block has either

a gain of 20 or 10 and must have sufficient headroom/

footroom to operate correctly.

As the nominal, VRSENSE is ±0.5 V for the full-scale specified

current flowing for all ranges. If this is gained by 20, the

measure current amplifier output (internal node) voltage

range is ±10 V with full-scale current and the default offset

DAC setting. The measure current block needs ±2.25 V

footroom/headroom for correct operation in addition to

the ±0.5 V VRSENSE.

For simplicity, when VREF = 5 V, minimum |AVDD − AVSS| =

31.125 V (VREF × 5.125 + headroom + footroom); otherwise,

there can be unanticipated effects resulting from headroom/

footroom issues. This does not take into account cable loss or

DUTGND contributions.

Similarly, when VREF = 2.5 V, minimum |AVDD − AVSS| = 18.3 V

and, when VREF = 2 V, minimum |AVDD − AVSS| = 16 V.

The AD5560 is designed to settle fast into large capacitive loads;

therefore, when slewing, the device draws 2× to 3× the current

range from the AVDD/AVSS supplies. When supply rails are

chosen, they should be capable of supplying each DPS channel

with sufficient current to slew.

CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS

Selection of HCAVSSx and HCAVDDx supplies is determined by

the EXTFORCE1 and EXTFORCE2 output ranges. The supply

rails chosen must take into account headroom and footroom,

DUTGND voltage range, cable loss, supply tolerance, and

VRSENSE. If diodes are used in series with the HCAVSSx and

HCAVDDx supplies pins (shown in Figure 60), the diode voltage

drop should also be factored into the supply rail calculation.

The AD5560 is designed to settle fast into large capacitive loads

in high current ranges; therefore, when slewing, the device draws

2× to 3× the current range from the HCAVSSx and HCAVDDx

supplies. When choosing supply rails, ensure that they are

capable of supplying each DPS channel with sufficient current

to slew.

All output stages of the AD5560 are symmetrical; they can

source and sink the rated current. Supply design/bypassing

should account for this.

POWER DISSIPATION

The maximum power dissipation allowed in the EXTFORCE1

stage is 10 W, whereas in the EXTFORCE2 stage, it is 5 W.

Take care to ensure that the device is adequately cooled to

remove the heat. The quiescent current is ~0.8 W with an

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