AD7927 datasheet(25/29 Pages) AD

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AD7927

Data Sheet

Rev. D | Page 24 of 28

MICROPROCESSOR INTERFACING

The serial interface on the AD7927 allows the part to be directly

connected to a range of many different microprocessors. This

section explains how to interface the AD7927 with some of the

more common microcontroller and DSP serial interface protocols.

AD7927 TO TMS320C541

The serial interface on the TMS320C541 uses a continuous serial

clock and frame synchronization signals to synchronize the

data transfer operations with peripheral devices like the AD7927.

The CS input allows easy interfacing between the TMS320C541

and the AD7927 without any glue logic required. The serial port

of the TMS320C541 is set up to operate in burst mode with inter-

nal CLKX0 (TX serial clock on Serial Port 0) and FSX0 (TX

frame sync from Serial Port 0). The serial port control register

(SPC) must have the following setup: FO = 0, FSM = 1, MCM =

1, and TXM = 1. The connection diagram is shown in Figure 29.

It should be noted that for signal processing applications, it is

imperative that the frame synchronization signal from the

TMS320C541 provides equidistant sampling. The VDRIVE pin

of the AD7927 takes the same supply voltage as that of the

TMS320C541. This allows the ADC to operate at a higher

voltage than the serial interface, that is, TMS320C541, if

necessary.

CLKX

CLKR

FSX

FSR

SCLK

DOUT

DIN

VDRIVE

TMS320C541*

VDD

*ADDITIONAL PINS REMOVED FOR CLARITY.

AD7927*

Figure 29. Interfacing to the TMS320C541

AD7927 TO ADSP-21xx

The ADSP-21xx family of DSPs is interfaced directly to the

AD7927 without any glue logic required. The VDRIVE pin of the

AD7927 takes the same supply voltage as that of the ADSP-218x.

This allows the ADC to operate at a higher voltage than the

serial interface, that is, ADSP-218x, if necessary.

The SPORT0 control register should be set up as follows:

TFSW = RFSW = 1, alternate framing

INVRFS = INVTFS = 1, active low frame signal

DTYPE = 00, right justify data

SLEN = 1111, 16-bit data-words

ISCLK = 1, internal serial clock

TFSR = RFSR = 1, frame every word

IRFS = 0

ITFS = 1

The connection diagram is shown in Figure 30. The ADSP-218x

has the TFS and RFS of the SPORT0 tied together, with TFS set

as an output and RFS set as an input. The DSP operates in alter-

nate framing mode and the SPORT0 control register is set up as

described. The frame synchronization signal generated on the

TFS is tied to CS, and as with all signal processing applications

equidistant sampling is necessary. However, in this example, the

timer interrupt is used to control the sampling rate of the ADC,

and under certain conditions, equidistant sampling may not be

achieved.

SCLK

RFS

TFS

SCLK

DOUT

DIN

ADSP-218x*

AD7927*

VDRIVE

VDD

*ADDITIONAL PINS REMOVED FOR CLARITY.

Figure 30. Interfacing to the ADSP-218x

The timer register, for instance, is loaded with a value that

provides an interrupt at the required sample interval. When

an interrupt is received, a value is transmitted with TFS or DT,

(ADC control word). The TFS is used to control the RFS and

therefore the reading of data. The frequency of the serial clock

is set in the SCLKDIV register. When the instruction to transmit

with TFS is given (that is, AX0 = TX0), the state of the SCLK is

checked. The DSP waits until the SCLK has gone high, low, and

high before transmission starts. If the timer and SCLK values

are chosen such that the instruction to transmit occurs on or

near the rising edge of SCLK, then the data may be transmitted

or it may wait until the next clock edge.

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