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LTC4259A датащи(PDF) 4 Page - Linear Technology |
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LTC4259A датащи(HTML) 4 Page - Linear Technology |
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4 / 32 page ![]() LTC4259A 4 4259Af Note 7: The LTC4259A is designed to maintain a port voltage of –46.6V to –57V and the VEE supply voltage range accounts for the drop across the diode, MOSFET and sense resistor. Note 8: VEE supply current, while classifying a short, is measured indirectly by measuring the DETECT n pin current while classifying a short. Note 9: The LTC4259A implements overload current detection per IEEE 802.3af. The minimum overload current (ICUT) is dependent on port voltage; ICUT_MIN = 15.4W/VPORT_MIN. An IEEE compliant system using the LTC4259A should maintain port voltage above –46.6V. Note 10: Unless otherwise specified, AC disconnect specifications require the following conditions: the DETECT pin is connected to the port as shown in Figure 1, a valid sine wave is applied to OSCIN, the OSCFAIL bit is cleared and the AC Disconnect Enable bits are set. Note 11: Guaranteed by design, not subject to test. Note 12: Values measured at VILD and VIHD. Note 13: If fault occurs during an I2C transaction, the INT pin will not be pulled down until a stop condition is present on the I2C bus. Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: DGND and AGND should be tied together in normal operation. Note 3: An internal clamp limits the GATE pins to a minimum of 12V above VEE. Driving this pin beyond the clamp may damage the part. Note 4: When a port powers on or off, the transient voltage on the port couples through CDET (Figure 16). The LTC4259A contains internal protection circuitry to withstand transient currents of up to 80mA for 5ms. As long as the absolute value of the current remains below 80mA, the LTC4259A will keep the voltage at the DETECT n pin within the absolute maximum voltage range. A properly sized RDET should limit the current to less than 60mA. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125 °C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 6: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground (AGND and DGND) unless otherwise specified. ELECTRICAL CHARACTERISTICS The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = –48V unless otherwise noted (Note 6). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tICUT Maximum Current Limit Duration After tICUT1 = 0, tICUT0 = 0 (Figure 3) q 50 60 70 ms Port Start-Up tICUT1 = 0, tICUT0 = 1 q 25 30 35 ms tICUT1 = 1, tICUT0 = 0 q 100 120 140 ms tICUT1 = 1, tICUT0 = 1 q 200 240 280 ms DCCLMAX Maximum Current Limit Duty Cycle Reg16h = 00h q 5.8 6.3 6.7 % tDIS Disconnect Delay tDIS1 = 0, tDIS0 = 0 (Figures 4, 5) q 300 360 400 ms tDIS1 = 0, tDIS0 = 1 q 75 90 100 ms tDIS1 = 1, tDIS0 = 0 q 150 180 200 ms tDIS1 = 1, tDIS0 = 1 q 600 720 800 ms tVMIN DC Disconnect Minimum Pulse VSENSEn – VEE > 5mV, VOUTn = –48V (Figure 4) q 0.02 1 ms Width Sensitivity (Note 11) I2C Timing fSCLK Clock Frequency (Note 11) q 400 kHz t1 Bus Free Time Figure 6 (Notes 11, 12) q 1.3 µs t2 Start Hold Time Figure 6 (Notes 11, 12) q 600 ns t3 SCL Low Time Figure 6 (Notes 11, 12) q 1.3 µs t4 SCL High Time Figure 6 (Notes 11, 12) q 600 ns t5 Data Hold Time Figure 6 (Notes 11, 12) q 150 ns t6 Data Set-Up Time Figure 6 (Notes 11, 12) q 200 ns t7 Start Set-Up Time Figure 6 (Notes 11, 12) q 600 ns t8 Stop Set-Up Time Figure 6 (Notes 11, 12) q 600 ns tr SCL, SDAIN Rise Time Figure 6 (Notes 11, 12) q 20 300 ns tf SCL, SDAIN Fall Time Figure 6 (Notes 11, 12) q 20 150 ns tFLTINT Fault Present to INT Pin Low (Notes 11, 12, 13) q 20 150 ns tSTOPINT Stop Condition to INT Pin Low (Notes 11, 12, 13) q 60 200 ns tARAINT ARA to INT Pin High Time (Notes 11, 12) q 20 300 ns |
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