LTC4259A datasheet(21/32 Pages) LINER

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LTC4259A

4259Af

at their rated voltage. Operated at half their rated voltage,

X7R capacitors exhibit more than 80% of their specified

capacitance. With other ceramic dielectrics commonly

used in 50V and 100V chip capacitors, capacitance falls

much more dramatically with voltage. At their rated volt-

age, Y5V or Z5U capacitors exhibit less than 30% of their

zero-bias capacitance. Ceramic capacitors can also have

significantly less capacitance at elevated temperatures. In

order to produce the desired capacitance at the operating

bias, 100V or 250V X7R capacitors should be used with

the LTC4259A.

As illustrated in Figure 17, the Power over Ethernet con-

nection between the PSE and PD includes a large amount

of capacitance. Cable capacitance is particularly troubling

because CAT-3 and CAT-5 pair-to-pair capacitance is not

tightly specified by the IEEE 802.3 standard or well con-

trolled by cable manufacturers. Considering that patch

panels, additional connectors, old wiring, etc. are likely to

be placed between the PSE and PD, pair-to-pair capaci-

tance is a pretty nebulous quantity. Consequently, the

cable’s contribution to the port impedance (at the fre-

quency used for AC disconnect) can be a concern.

Assumimg that fOSCIN is 100Hz, the 0.1µF of CPSE plus

0.05

µF of cable capacitance gives a port impedance of 10k

at 100Hz. The PD AC signature resistance is about 25k.

Connecting a PD with the maximum allowed resistance of

26.25k brings the connection impedance to about 8k. The

presence of a PD only makes a 20% reduction in the port

impedance requiring the AC disconnect circuitry to be

quite sensitive. When the OSCIN pin is driven with a sine

wave, the LTC4259A is able to distinguish between capaci-

tive impedance and resistive impedance on the Power over

Ethernet connection. AC disconnect is reliable for cable

capacitance up to about 0.2

µF, nearly an order of magni-

tude greater than worst case for a long CAT-3 or CAT-5

cable.

APPLICATIO S I FOR ATIO

Figure 16. AC Disconnect Single Port Application Circuit (Port 4 Shown)

Figure 17. Simplified AC Disconnect Circuit with Impedances at 100Hz

LEVEL

SHIFT

DETECT4

AGND

DGND

OSCIN

1/4

LTC4259A

–48V

GND

OUT4

ROUT4

10k

RS4

0.5

Ω 1%

DDET4

CMPD3003

RDET4

Rpd_d

≤26.25k

Cpd_d

≥0.05µF

CDET4

0.47

µF

100V X7R

CPSE4

0.1

µF

100V X7R

4259A F16

DAC4

S1B

GATE4

SENSE4

VEE

OSCILLATOR

INPUT

CURRENT

SENSE

RDET

ZLINK < 14k

ZCABLE < 32k

~16k

~7k

ZPD < 14k

CDET

0.47

µF

CPSE

0.10

µF

CCABLE ≤ 0.05µF

<32k

Cpd_d ≥ 0.05µFRpd_d < 26.25k

4259A F17

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