LTC4259A datasheet(22/32 Pages) LINER

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LTC4259A

4259Af

OSCIN Input and Oscillator Requirements

AC disconnect depends on an external oscillator source

applied to the OSCIN pin. The LTC4259A measures port

impedance by applying an amplified version of the OSCIN

signal to the port’s DETECT pin (see Figure 16). The

oscillator should be well-controlled because errors in this

signal become errors in the measured port impedance. As

shown in Figure 17, the load being sensed by AC discon-

nect has a resistive and a large reactive component.

Current through the PD’s signature resistor depends on

the amplitude of the AC signal while current into the

capacitors depends on the slew rated: I = C • dV/dt.

Consequently, the LTC4259A is sensitive to the amplitude

and slew rate of the OSCIN signal, but is more tolerant of

frequency and offset errors. Internal limits prevent the

LTC4259A from being adversely affected by OSCIN sig-

nals with excessive amplitude.

There are many ways to build oscillators with controlled

amplitudes and slew rates, especially since the frequency

of the oscillator does not have to be well-controlled.

Contact the LTC Applications department for oscillator

circuits.

As alluded to previously, AC disconnect is complicated

and redesigning for different component sizes is a difficult

task. For optimum performance, use the recommended

component values and drive OSCIN with a 100Hz 2VP-P,

1.2V offset sine wave. Keep in mind that the IEEE 802.3af

specification places upper limits of 100V/ms on the slew

rate and 500Hz on the frequency of the AC signal at the

port. Voltage gain, AVACD, from OSCIN to DETECTn in-

creases the slew rate by the voltage gain. Since AVACD has

a maximum absolute value of 3.3V/V (

±3V typ), the slew

rate at the OSCIN pin must be less than 30V/ms. A slew

rate around 0.6V/ms at OSCIN will work with the recom-

mended values of CDET, RDET and CPSE.

The LTC4259A’s OSCIN input amplifier will accept signals

between DGND – 0.3V and VDD + 0.5V. This amplifier has

a gain of –1 and is referenced to 1.2V above DGND. An

OSCIN voltage greater than 2.2V will cause the amplifier’s

output to clip against DGND. Clipping will not affect the

performance of AC disconnect until the clipping becomes

so severe that even the midrange (where the controlled

slew rate occurs) of the signal is clipped. Keep the midrange

or average voltage of the OSCIN signal between 0.9V and

1.5V to avoid severe clipping. OSCIN signals below DGND

can interact with the ESD protection circuitry on the pin

and are not recommended. Also, meeting the IEEE 802.3af

specification for maximum AC amplitude on the port just

after the PD is removed depends on the OSCIN input peak-

to-peak amplitude. Clipping by LTC4259A’s OSCIN input

circuitry will generally ensure that this specification is not

exceeded. Note that under normal operation, the AC dis-

connect output on the DETECT

n pin will have an amplitude

near 6V peak-to-peak. The combination of RDET, CDET and

CPSE attenuate the signal so roughly half this amplitude is

seen at the port when the port is powered and the PD has

just been removed. When the PD is still connected there

will be almost no AC signal at the port.

The LTC4259A monitors Pin 36 for the presence of an

oscillating signal. If no signal is present and the Osc Fail

Mask bit is set, then Osc Fail (bit 1 of the Supply Event

AC disconnect circuitry self-checks the OSCIN signal, the

Osc Fail bit is intended as a fault indicator to alert the PSE

host controller. The Osc Fail bit has no effect beyond

triggering the interrupt. A clear Osc Fail bit indicates that

the OSCIN signal goes below 0.6V and above 1.8V at least

once every 250ms. It does not necessarily guarantee that

AC disconnect will function properly. However, AC discon-

nect itself is a more thorough test of the OSCIN signal.

When the OSCIN signal is either absent or corrupted,

powered ports with AC disconnect enabled (and DC dis-

connect not enabled) will automatically disconnect. After

the LTC4259A is reset (by power on, Reset All bit or the

RESET pin) the Osc Fail bit is set. Once the Osc Fail bit is

cleared, it will only be set by an invalid signal on the OSCIN

pin or another reset.

APPLICATIO S I FOR ATIO

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