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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9864-EBZ датащи(PDF) 6 Page - Analog Devices |
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AD9864-EBZ датащи(HTML) 6 Page - Analog Devices |
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6 / 48 page  Data Sheet AD9864 Rev. A | Page 5 of 47 DIGITAL SPECIFICATIONS VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS, fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins. Table 2. Parameter Temperature Test Level Min Typ Max Unit DECIMATOR Decimation Factor1 Full IV 48 960 Pass-Band Width Full V 50% fCLKOUT Pass-Band Gain Variation Full IV 1.2 dB Alias Attenuation Full IV 88 dBm SPI READ OPERATION (See Figure 30) PC Clock Frequency Full IV 10 MHz PC Clock Period (tCLK) Full IV 100 ns PC Clock High (tHI) Full IV 45 ns PC Clock Low (tLOW) Full IV 45 ns PC to PD Setup Time (tDS) Full IV 2 ns PC to PD Hold Time (tDH) Full IV 2 ns PE to PC Setup Time (tS) Full IV 5 ns PC to PE Hold Time (tH) Full IV 5 ns SPI WRITE OPERATION2 (See Figure 29) PC Clock Frequency Full IV 10 MHz PC Clock Period (tCLK) Full IV 100 ns PC Clock High (tHI) Full IV 45 ns PC Clock Low (tLOW) Full IV 45 ns PC to PD Setup Time (tDS) Full IV 2 ns PC to PD Hold Time (tDH) Full IV 2 ns PC to PD (or DOUTB) Data Valid Time (tDV) Full IV 3 ns PE to PD Output Valid to High-Z (tEZ) Full IV 8 ns SSI2 (See Figure 33) CLKOUT Frequency Full IV 0.867 26 MHz CLKOUT Period (tCLK) Full IV 38.4 1153 ns CLKOUT Duty Cycle (tHI, tLOW) Full IV 33 50 67 ns CLKOUT to FS Valid Time (tV) Full IV −1 +1 ns CLKOUT to DOUT Data Valid Time (tDV) Full IV −1 +1 ns CMOS LOGIC INPUTS3 Logic 1 Voltage (VIH) Full IV 0.7 × VDDH V Logic 0 Voltage (VIL) Full IV 0.3 × VDDH V Logic 1 Current (IIH) Full IV 10 µA Logic 0 Current (IIL) Full IV 10 µA Input Capacitance Full IV 3 pF CMOS LOGIC OUTPUTS2, 3,4 Logic 1 Voltage (VOH) Full IV VDDH − 0.2 V Logic 0 Voltage (VOL) Full IV 0.2 V 1 Programmable in steps of 48 or 60. 2 CMOS output mode with CLOAD = 10 pF and drive strength = 7. 3 Absolute maximum and minimum input/output levels are VDDH + 0.3 V and −0.3 V. 4 IOL = 1 mA; specification is also dependent on drive strength setting. |
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