AD9864-EBZ datasheet(43/48 Pages) AD

43 / 48 page

AD9864

Data Sheet

Rev. A | Page 42 of 47

rated operating range of 13 MHz to 26 MHz and no significant

spurious products related to fCLK fall within the desired pass band,

resulting in a reduction in sensitivity performance. If a spurious

component is found to limit the sensitivity performance, the

decimation factor can often be modified slightly to find a

spurious free pass band. Selecting a higher fCLK is typically more

desirable given a choice, because the filtering requirements of

the first IF often depend on the transition region between the IF

frequency and the image band (±fCLK/4). Lastly, the output SSI

clock rate, fCLKOUT, and digital driver strength must be set to their

lowest possible settings to minimize the potential harmful

effects of digital induced noise while preserving a reliable data

link to the DSP. Note that the SSICRA, SSICRB, and SSIORD

registers (0x18, 0x19, and 0x1A) provide a large degree of

flexibility for optimization of the SSI interface.

Synchronization of Multiple AD9864 Devices

Some applications, such as receiver diversity and beam steering,

may require two or more AD9864 devices operating in parallel

while maintaining synchronization. Figure 73 shows an example

of how multiple AD9864 devices can be cascaded, with one device

serving as the master and the other devices serving as the slaves.

In this example, all of the devices have the same SPI register

configuration since they share the same SPI interface to the

DSP. Because the state of each of the internal counters of the

AD9864 devices is unknown upon initialization, synchronization

of the devices is required via a SYNCB pulse (see Figure 37) to

synchronize their digital filters and to ensure precise time

alignment of the data streams.

Although the synthesizers of all of the device are enabled, the

LO and CLK signals for the slave(s) are derived from the

synthesizers of the master and are referenced to an external

crystal oscillator. All of the necessary external components (the

loop filters, varactor, LC, and VCO) required to ensure proper

closed-loop operation of the master synthesizers are included.

Note that the FREF input of the slave devices must be tied to

ground.

Note that although the VCO output of the LO synthesizer is ac-

coupled to the LO input(s) of the slave, all of the CLK inputs of

the devices must be dc-coupled if the CLK oscillators of the

AD9864 are enabled. This is because of the dc current required

by the CLK oscillators in each device. In essence, these negative

impedance cores are operating in parallel, increasing the

effective Q of the LC resonator circuit. RBIAS must be sized such

that the sum of the dc bias currents of the oscillators maintains

a common-mode voltage of approximately 1.6 V.

VCO

DOUTA

CLKOUT

FREF

CLKP

CLKN

LOP

LON

IFIN

AD9864

MASTER

IOUTC

LOOP

FILTER

IOUTC

LOP

LON

IFIN

DOUTA

CLKOUT

SYNCB

DSP

CLKP

CLKN

IOUTL

TO DSP

FROM

DSP

LOOP

FILTER

CVAR

0.1µF

LOSC

RBIAS

COSC

TO OTHER

AD9864s

FROM

CRYSTAL

OSCILLATION

VDDC

TO OTHER

AD9864s

AD9864

SLAVE

FREF

SYNCB

Figure 74. Example of Synchronizing Multiple AD9864 Devices

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