AD9864-EBZ datasheet(35/48 Pages) AD

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AD9864

Data Sheet

Rev. A | Page 34 of 47

VGA

DAC

Σ-Δ ADC

DEC1

÷12

DEC2

AND

DEC3

I + Q

SELECT

LARGER

AGCR

REF LEVEL

AGCA/AGCD

SCALING

CDAC

GCP

(1 – Z–1)

AGCV

SETTING

DVGA

RSSI DATA

TO SSI

I/Q DATA

TO SSI

Figure 59. Functional Block Diagram of VGA and AGC

Variable Gain Control

The variable gain control is enabled by setting the AGCR field

of Register 0x06 to 0. In this mode, the gain of the VGA (and

the DVGA) can be adjusted by writing to the 16-bit AGCG

the SPI port is fCLK/240. The MSB of this register is the bit that

enables 16 dB of attenuation in the mixer. This feature allows

the AD9864 to cope with large level signals beyond the VGA

range (that is, > −18 dBm at LNA input) to prevent overloading

of the ADC.

The lower 15 bits specify the attenuation in the remainder of the

signal path. If the DVGA is enabled, the attenuation range is

from −12 dB to +12 dB because the DVGA provides 12 dB of

digital gain. In this case, all 15 bits are significant. However,

with the DVGA disabled, the attenuation range extends from

0 dB to 12 dB and only the lower 14 bits are useful. Figure 60

shows the relationship between the amount of attenuation and

the AGC register setting for both cases.

AGCG SETTING (HEX)

–12

0000

1FFF

3FFF

7FFF

5FFF

–6

VGA

RANGE

DVGA

RANGE

ONLY

VGA ENABLED

DVGA AND

VGA ENABLED

Figure 60. AGC Gain Range Characteristics vs. AGCG Register

Setting With and Without DVGA Enabled

Referring to Figure 59, the gain of the VGA is set by an 8-bit

control DAC that provides a control signal to the VGA

appearing at the gain control pin (GCP). For applications

implementing automatic gain control, the output resistance of

the DAC can be reduced by a factor of 9 to decrease the attack

time of the AGC response for faster signal acquisition. An

external capacitor, CDAC, from GCP to analog ground is

required to smooth the output of the DAC each time it updates

as well as to filter wideband noise. Note that CDAC, in

combination with the programmable output resistance of the

DAC, sets the −3 dB bandwidth and time constant associated

with this RC network.

A linear estimate of the received signal strength is performed at

the output of the first decimation stage (DEC1) and output of

the DVGA (if enabled), as discussed in the AGC section. This

data is available as a 6-bit RSSI field within an SSI frame with 60

corresponding to a full-scale signal for a given AGC attenuation

setting. The RSSI field is updated at fCLK/60 and can be used

with the 8-bit attenuation field (or AGCG attenuation setting)

to determine the absolute signal strength. Note that the RSSI data

must be post filtered to remove the ac ripple component that is

dependent on the frequency offset relative to the IF frequency.

The accuracy of the mean RSSI reading (relative to the IF input

power) depends on the input signal’s frequency offset relative to

the IF frequency because both the response of the DEC1 filter

as well as the signal transfer function of the ADC attenuate the

downconverted signal level of the mixer, centered at fCLK/8. As a

result, the estimated signal strength of input signals falling

within proximity to the IF is reported accurately, while those

signals at increasingly higher frequency offsets incur larger

measurement errors. Figure 61 shows the normalized error of

the RSSI reading as a function of the frequency offset from the

IF frequency. Note that the significance of this error becomes

apparent when determining the maximum input interferer (or

blocker) levels with the AGC enabled.

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