MFC2000 datasheet(144/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

6-2

Conexant

100723A

6.2

Fax Timing Logic

The fax timing logic block generates all of the time bases needed by the MFC2000. The fax timing logic block

diagram is provided in Figure 6-1.

(1) I_LCLPHI is only used internally to indicate the SIUCLK cycle before the last SIUCLK cycle in one ICLK time period.

(2) IHS_LCLPHI is only used internally to indicate the SIUCLK cycle before the last SIUCLK cycle in one IHSCLK time period.

(3) ICLK is the base clock for internal peripherals and is only used internally to synchronize all the internal logic. The

frequency of ICLK must be equal to or less than 10MHz. ICLK duty cycle is 33% when ICLK = SIUCLK/3.

(4) IHSCLK is the high speed base clock for the PIO and Bit Rotation blocks and is only used internally to synchronize all the

internal logic. The frequency of IHSCLK must be equal to or less than 20MHz.

(5) AUXCLK has the same frequency as ICLK and is output to the external world through a pin. AUXCLK is used to

synchronize external peripherals. AUXCLK duty cycle is always 50% no matter what is the relationship between ICLK and

SIUCLK.

(6) MMCLK is the base clock for the motor control logic.

(7) TIM_8MS is used by the PIO Block.

(8) TIM_1MS is the base clock for the the watchdog timer.

(9) TIM_MSINT is used to synchronize the scanning and motor stepping.

(10) TIM_1MS/2MSIRQ is used to generate an interrupt every 1ms or 2ms (selectable). The actual period of the 1MSIRQ =

1.00708 ms and 2MSIRQ = 2.01416ms

Notes:

(from RTC)

MMCLK

ONEMSCLK

TIM_1MS/2MSIRQ

SIUCLK

Divide

By 8

Divide

By B

B= [ICLK period]+1

B is from 2 to 4

ICLKand

AUXCLK

Divide

By C

C= [Prescaler]+1

C is from 1 to 256

Divide

By D

D= [MSINT

perild]+1

D is from 1 to 64

WATCHDOG

TIMING

GENERATOR

TIM_MSINT

1MS/2MSIRQ

GENERATOR

TIM_1MS_SIUCLK

Divide

By A

IHS_LCLPHI

IHSCLK

A= [IHSCLK

period]+1

A is from 1 to 2

I_LCLPHI

TIM_125US_SIUCLK

IHSCK1X_SELn

Divide

By 8

TIM_8MS

TIM_125US_ICLK

Figure 6-1. Fax Timing Control Logic Block Diagram

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