 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
AD9684 датащи(PDF) 11 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9684 датащи(HTML) 11 Page - Analog Devices |
|
|
11 / 65 page  AD9684 Data Sheet Rev. 0 | Page 10 of 64 CLK+ DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST SYNC+ APERTURE DELAY N N + x N + 36 N + 37 N + 38 D13± D0± CONVERTER 0 SAMPLE [N] VIN±x STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS D13 D13 D13 D13 D13 D13 D13 D0 D0 D0 D0 D0 D0 D0 CLK– SYNC– STATUS+ (OVERRANGE/STATUS BIT) STATUS– tCLK tDCO CONSTANT LATENCY = X CLK CYCLES tPD tSKEWF tSKEWR CONVERTER 1 SAMPLE [N] CONVERTER 0 SAMPLE [N + 1] CONVERTER 1 SAMPLE [N + 1] CONVERTER 0 SAMPLE [N + 2] SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET STATUS BIT SELECTED BY REGISTER 0x559, BITS[2:0] IN THE REGISTER MAP D13 D0 Figure 5. Parallel Interleaved Mode—Two Converters, ≤14-Bit Data, Output Sample Rate < 625 MSPS |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
