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AD9684

Data Sheet

MULTICHIP SYNCHRONIZATION

The AD9684 has a SYNC± input that allows the user flexible

options for synchronizing the internal blocks. The SYNC±

input is a source synchronous system reference signal that

enables multichip synchronization. The input clock divider,

DDCs, and signal monitor block LVDS output link can be

synchronized using the SYNC± input. For the highest level of

timing accuracy, SYNC± must meet the setup and hold

requirements relative to the CLK± input.

The flowchart in Figure 67 shows the internal mechanism by

which multichip synchronization can be achieved in the AD9684.

The AD9684 supports several features that aid users in meeting

the requirements for capturing SYNC± signals. The SYNC±

sample event can be defined as either a synchronous low to high

transition or a synchronous high to low transition. Additionally,

the AD9684 allows the SYNC± signal to be sampled using

either the rising edge or the falling edge of the CLK± input. The

AD9684 can also to ignore a programmable number (up to 16)

of SYNC± events. The SYNC± control options can be selected

using Register 0x120 and Register 0x121.

YES

UPDATE

SETUP/HOLD

DETECTOR STATUS

REG (0x128)

INCREMENT

SYNC± IGNORE

COUNTER

YES

SYNC±

ENABLED?

REG (0x120)

CLOCK

DIVIDER

> 1?

REG (0x10B)

YES

INPUT

CLOCK

DIVIDER

ALIGNMENT

REQUIRED?

YES

ALIGN CLOCK

DIVIDER

PHASE TO

SYNC±

DDC NCO

ALIGNMENT

ENABLED?

REG (0x300)

RESET

SYNC± IGNORE

COUNTER

START

SYNC±

ASSERTED?

YES

ALIGN SIGNAL

MONITOR

COUNTERS

YES

INCREMENT

SYNC±

COUNTER

REG (0x12A)

BACK TO START

SYNC±

IGNORE

COUNTER

EXPIRED?

REG (0x121)

CLOCK

DIVIDER

AUTO ADJUST

ENABLED?

REG (0x10D)

SIGNAL

MONITOR

SYNC

ENABLED?

REG (0x26F)

ALIGN PHASE OF ALL

INTERNAL CLOCKS

TO SYNC±

YES

CLOCK

ALIGNMENT

REQUIRED?

ALIGN DDC

NCO PHASE

ACCUMULATOR

Figure 67. Multichip Synchronization

Rev. 0 | Page 48 of 64

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