LTC3703 datasheet(28/32 Pages) LINER

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LTC3703

3703f

Using the above calculation for bottom MOSFET TJ, the

max RDS(ON) = (25mΩ/2) [1 + 0.009 (105-25)] = 21.5mΩ

Therefore, IMAX pin voltage should be set to (10A)(0.0215)

= 0.215V. The RSET resistor can now be chosen to be

0.215V/12

µA = 18kΩ.

CIN is chosen for an RMS current rating of about 5A (IMAX/

2) at 85

°C. For the output capacitor, two low ESR OSCON

capacitors (18m

Ω each) are used to minimize output

voltage changes due to inductor current ripple and load

steps. The ripple voltage will be:

∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (4A)(0.018Ω/2)

= 36mV

However, a 0A to 10A load step will cause an output

voltage change of up to:

∆VOUT(STEP) = ∆ILOAD(ESR) = (10A)(0.009Ω)

= 90mV

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3703. These items are also illustrated graphically in

the layout diagram of Figure 18. For layout of a Boost Mode

Converter, layout is similar with VIN and VOUT swapped.

Check the following in your layout:

1. Keep the signal and power grounds separate. The signal

ground consists of the LTC3703 GND pin, the ground

return of CVCC, and the (–) terminal of VOUT. The power

ground consists of the Schottky diode anode, the source

of the bottom side MOSFET, and the (–) terminal of the

input capacitor and DRVCC capacitor. Connect the signal

and power grounds together at the (–) terminal of the

output capacitor. Also, try to connect the (–) terminal of

the output capacitor as close as possible to the (–)

terminals of the input and DRVCC capacitor and away from

the Schottky loop described in (2).

2. The high di/dt loop formed by the top N-channel

MOSFET, the bottom MOSFET and the CIN capacitor

should have short leads and PC trace lengths to minimize

high frequency noise and voltage stress from inductive

ringing.

3. Connect the drain of the top side MOSFET directly to the

(+) plate of CIN, and connect the source of the bottom side

MOSFET directly to the (–) terminal of CIN. This capacitor

provides the AC current to the MOSFETs.

4. Place the ceramic CDRVCC decoupling capacitor imme-

diately next to the IC, between DRVCC and BGRTN. This

capacitor carries the MOSFET drivers’ current peaks.

Likewise the CB capacitor should also be next to the IC

between BOOST and SW.

5. Place the small-signal components away from high

frequency switching nodes (BOOST, SW, TG, and BG). In

the layout shown in Figure 20, all the small signal compo-

nents have been placed on one side of the IC and all of the

power components have been placed on the other. This

also helps keep the signal ground and power ground

isolated.

6. A separate decoupling capacitor for the supply, VCC, is

useful with an RC filter between the DRVCC supply and VCC

pin to filter any noise injected by the drivers. Connect this

capacitor close to the IC, between the VCC and GND pins

and keep the ground side of the VCC capacitor (signal

ground) isolated from the ground side of the DRVCC

capacitor (power ground).

7. For optimum load regulation and true remote sensing,

the top of the output resistor divider should connect

independently to the top of the output capacitor (Kelvin

connection), staying away from any high dV/dt traces.

Place the divider resistors near the LTC3703 in order to

keep the high impedance FB node short.

APPLICATIO S I FOR ATIO

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