LTC3703 datasheet(25/32 Pages) LINER

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LTC3703

3703f

oscillator can synchronize to frequencies between 100kHz

and 600kHz, independent of the frequency programmed

by the RSET resistor. However, it is recommended that an

RSET resistor be chosen such that the frequency pro-

grammed by the RSET resistor is close to the expected

frequency of the external clock. In this way, the best

converter operation (ripple, component stress, etc) is

achieved if the external clock signal is lost.

Minimum On-Time Considerations (Buck Mode)

Minimum on-time tON(MIN) is the smallest amount of time

that the LTC3703 is capable of turning the top MOSFET on

and off again. It is determined by internal timing delays and

the amount of gate charge required to turn on the top

MOSFET. Low duty cycle applications may approach this

minimum on-time limit and care should be taken to ensure

that:

OUT

ON MIN

•

()

where tON(MIN) is typically 200ns.

If the duty cycle falls below what can be accommodated by

the minimum on-time, the LTC3703 will begin to skip

cycles. The output will be regulated, but the ripple current

and ripple voltage will increase. If lower frequency opera-

tion is acceptable, the on-time can be increased above

tON(MIN) for the same step-down ratio.

Pin Clearance/Creepage Considerations

The LTC3703 is available in two packages (GN16 and G28)

both with identical functionality. The GN16 package gives

the smallest size solution, however the 0.013” (minimum)

space between pins may not provide sufficient PC board

trace clearance between high and low voltage pins in

higher voltage applications. Where clearance is an issue,

the G28 package should be used. The G28 package has 4

unconnected pins between the all adjacent high voltage

and low voltage pins, providing 5(0.0106”) = 0.053”

clearance which will be sufficient for most applications up

to 100V. For more information, refer to the printed circuit

board design standards described in IPC-2221

(www.ipc.org).

APPLICATIO S I FOR ATIO

Efficiency Considerations

The efficiency of a switching regulator is equal to the

output power divided by the input power (x100%). Per-

cent efficiency can be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage

of input power. It is often useful to analyze the individual

losses to determine what is limiting the efficiency and

what change would produce the most improvement. Al-

though all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3703 circuits: 1) LTC3703 VCC current, 2)

MOSFET gate current, 3) I2R losses, 4) Topside MOSFET

transition losses.

1. VCC Supply current. The VCC current is the DC supply

current given in the Electrical Characteristics table which

powers the internal control circuitry of the LTC3703. Total

supply current is typically about 2.5mA and usually results

in a small (<1%) loss which is proportional to VCC.

2. DRVCC current is MOSFET driver current. This current

results from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched on and

then off, a packet of gate charge QG moves from DRVCC to

ground. The resulting dQ/dt is a current out of the DRVCC

supply. In continuous mode, IDRVCC = f(QG(TOP) + QG(BOT)),

where QG(TOP) and QG(BOT) are the gate charges of the top

and bottom MOSFETs.

3. I2R losses are predicted from the DC resistances of

MOSFETs, the inductor and input and output capacitor

ESR. In continuous mode, the average output current

flows through L but is “chopped” between the topside

MOSFET and the synchronous MOSFET. If the two

MOSFETs have approximately the same RDS(ON), then the

resistance of one MOSFET can simply be summed with the

DCR resistance of L to obtain I2R losses. For example, if

each RDS(ON) = 25mΩ and RL = 25mΩ, then total resis-

tance is 50m

Ω. This results in losses ranging from 1% to

5% as the output current increases from 1A to 5A for a 5V

output.

4. Transition losses apply only to the topside MOSFET in

buck mode and they become significant when operating at

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