LTC3703 datasheet(18/32 Pages) LINER

18 / 32 page

LTC3703

3703f

Bottom MOSFET Source Supply (BGRTN)

The bottom gate driver, BG, switches from DRVCCtoBGRTN

where BGRTN can be a voltage between ground and –5V.

Why not just keep it simple and always connect BGRTN to

ground? In high voltage switching converters, the switch

node dV/dt can be many volts/ns, which will pull up on the

gate of the bottom MOSFET through its Miller capacitance.

If this Miller current, times the internal gate resistance of

the MOSFET plus the driver resistance, exceeds the thresh-

old of the FET, shoot-through will occur. By using a nega-

tive supply on BGRTN, the BG can be pulled below ground

when turning the bottom MOSFET off. This provides a few

extra volts of margin before the gate reaches the turn-on

threshold of the MOSFET. Be aware that the maximum

voltage difference between DRVCC and BGRTN is 15V. If,

for example, VBGRTN = –2V, the maximum voltage on

DRVCC pin is now 13V instead of 15V.

Current Limit Programming

Programming current limit on the LTC3703 is straight

forward. The IMAX pin sets the current limit by setting the

maximum allowable voltage drop across the bottom

MOSFET. The voltage across the MOSFET is set by its on-

resistance and the current flowing in the inductor, which

is the same as the output current. The LTC3703 current

limit circuit inverts the negative voltage across the MOSFET

before comparing it to the voltage at IMAX, allowing the

current limit to be set with a positive voltage.

To set the current limit, calculate the expected voltage

drop across the bottom MOSFET at the maximum desired

current and maximum junction temperature:

VPROG = (ILIMIT)(RDS(ON))(1 + δ)

where

δ is explained in the MOSFET Selection section.

VPROG is then programmed at the IMAX pin using the

internal 12

µA pull-up and an external resistor:

RIMAX = VPROG/12µA

The current limit value should be checked to ensure that

ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit

generally occurs with the largest VIN at the highest ambi-

ent temperature, conditions that cause the largest power

loss in the converter. Note that it is important to check for

self-consistency between the assumed MOSFET junction

temperature and the resulting value of ILIMIT which heats

the MOSFET switches.

Caution should be used when setting the current limit

based upon the RDS(ON) of the MOSFETs. The maximum

current limit is determined by the minimum MOSFET on-

resistance. Data sheets typically specify nominal and

maximum values for RDS(ON), but not a minimum. A

reasonable assumption is that the minimum RDS(ON) lies

the same amount below the typical value as the maximum

lies above it. Consult the MOSFET manufacturer for further

guidelines.

For best results, use a VPROG voltage between 100mV and

500mV. Values outside of this range may give less accu-

rate current limit. The current limit can also be disabled by

floating the IMAX pin.

FEEDBACK LOOP/COMPENSATION

Feedback Loop Types

In a typical LTC3703 circuit, the feedback loop consists of

the modulator, the external inductor, the output capacitor

and the feedback amplifier with its compensation network.

All of these components affect loop behavior and must be

accounted for in the loop compensation. The modulator

consists of the internal PWM generator, the output MOSFET

drivers and the external MOSFETs themselves. From a

feedback loop point of view, it looks like a linear voltage

transfer function from COMP to SW and has a gain roughly

equal to the input voltage. It has fairly benign AC behavior

at typical loop compensation frequencies with significant

phase shift appearing at half the switching frequency.

The external inductor/output capacitor combination makes

a more significant contribution to loop behavior. These

components cause a second order LC roll off at the output,

with the attendant 180

° phase shift. This rolloff is what

filters the PWM waveform, resulting in the desired DC

output voltage, but the phase shift complicates the loop

compensation if the gain is still higher than unity at the

pole frequency. Eventually (usually well above the LC pole

frequency), the reactance of the output capacitor will

approach its ESR and the rolloff due to the capacitor

will stop, leaving 6dB/octave and 90

° of phase shift

(Figure 11).

APPLICATIO S I FOR ATIO

LTC3703 датащи(PDF) 18 Page - Linear Technology

LTC3703 датащи(HTML) 18 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

датащи скачать

ссылки URL