ECT25S80 datasheet(17/45 Pages) E-CMOS

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E-CMOS Corp. (www.ecmos.com.tw)

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5B16N-Rev.F001

ECT25S80

8M BIT SPI NOR FLASH

Figure 7. Read Status Register Sequence Diagram

Write Status Register (01H)

See Figure 8, the Write Status Register instruction allows new values to be written to the Status

Write Enable instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register instruction has no effect on S15, S1 and S0 of the Status Register. /CS must be

driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register

instruction is not executed. If /CS is driven high after eighth bit of the data byte, the CMP and QE and SRP1

bits will be cleared to 0. As soon as /CS is driven high, the self-timed Write Status Register cycle (whose

duration is tW) is initiated.While the Write Status Register cycle is in progress, the Status Register may still be

read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-

timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write

Enable Latch is reset.

The Write Status Register instruction allows the user to change the values of the Block Protect (SEC, TB, BP2,

BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3. The Write

Status Register instruction also allows the user to set or reset he Status Register Protect (SRP1 and SRP0) bits

in accordance with the Write Protect (/WP) signal.The Status Register Protect (SRP1 and SRP0) bits and Write

Protect (/WP) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register

instruction is not executed once the Hardware Protected Mode is entered.

Figure 8. Write Status Register Sequence Diagram

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