ECT25S80 datasheet(7/45 Pages) E-CMOS

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E-CMOS Corp. (www.ecmos.com.tw)

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5B16N-Rev.F001

ECT25S80

8M BIT SPI NOR FLASH

Device Reset

In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power

reset

(POR) circuit is included. At Power-up, the device does not respond to any instruction until

VCC

has

reached

the

power

reset

threshold voltage(this threshold is lower than the minimum VCC operating

voltage defined in operating ranges). When VCC has passed the POR threshold, the device is reset.

Power-down

At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to

below the power on reset threshold voltage, the device stops responding to any be allowed to follow the

voltage applied on VCC) and in Standby Power mode (that is there should be no internal Write cycle in

progress).

Active Power and Standby Power Modes

When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device consumes

ICC.

When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the

device then goes in to the Standby Power mode, and the device consumption drops to ICC1.

Hold Condition

The Hold (/HOLD) signal is used to pause any serial communications with the device without resetting the

clocking sequence. During the Hold condition, the Serial Data Output(SO)is high impedance, and Serial Data

Input (SI) and Serial Clock (SCLK) are Don’t Care. To enter the Hold condition, the device must be selected,

with Chip Select(/CS) Low. Normally, the device is kept selected, for the whole duration of the Hold condition.

Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and

this mechanism can be used if it is required to reset any processes that had been in progress.

The Hold condition starts when the Hold (/HOLD) signal is driven Low at the same time as Serial Clock (SCLK)

already being Low (as shown in Figure 4).

The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C)

already being Low. Figure 4 also shows what happens if the rising and falling edges are not timed to coincide

with Serial Clock (SCLK) being Low.

Figure 4. Hold condition activation

Status Register

Status Register Table

See Table 3 and Table 4 for detail description of the Status Register bits. Status Register-2 (SR2) and Status

write enabled or disabled the state of write protection, Quad SPI setting, Security Register lock status, and

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