ADCS9888 datasheet(5/34 Pages) NSC

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Pin Descriptions (Continued)

Label

Type

Description

COAST

Digital Input PLL Clock Generator Coast Input. When enabled via Register 0Fh, Bit 5,

this input will cause the clock generator circuit to run open loop and ignore

the input reference clock. This is useful when operating with sync signals

that contain extra equalization pulses that must be ignored by the PLL. In

many cases, the internal VSOUT signal is used to provide the coast

control signal, but in some cases it is useful to provide an external COAST

control. Please refer to the applications section for more information.

CKEXT

Digital Input External Clock Input (Optional). This input can be used to provide an

external clock source instead of the internally generated clock. It is

enabled via Register 15h, Bit 0. When an external clock is used, most

other internal functions operate normally. When unused, this pin can be

connected to ground directly, or through a 10 k

Ω resistor. The sampling

phase adjustment feature is operational when CKEXT is used.

CKINV

Digital Input Sampling clock Inverting Input. This input can be used to invert the pixel

sampling clock, with respect to the normal phase of operation. This causes

the pixel sampling point to be shifted by 180 degrees in phase. Alternate

pixel sampling mode makes use of this feature by sampling at 1/2 the

incoming pixel rate, and switching the sampling phase by 180 degree

between alternate frames of video. When unused, this input should be

grounded. See the applications section for more information.

Serial Interface

SDA

Digital I/O

Serial Control Interface Data Input/Output. The serial interface is used to

access the configuration and status registers in the ADCS9888. Mode and

Data information are transferred through the SDA pin from the host or

master device. Please refer to the applications section of the datasheet

under Serial Communications for more information.

SCL

Digital Input Serial Control Interface Clock Input. The clock input is controlled by the

host or master device, and is used to load in the data sent by the host,

and to clock data out of the ADCS9888. Please refer to the applications

section of the datasheet under Serial Communications for more

information.

Digital Input The least significant bit of the device serial address is selectable as 0 or 1

to allow up to 2 ADCS9888 devices to be connected on the same serial

interface. Please refer to the applications section of the datasheet under

Serial Communications for more information.

Sync. Outputs

125

HSOUT

Digital

Output

Horizontal Sync Output. Internally generated and phase aligned horizontal

sync signal. This signal is used as a timing reference for the digital output

data stream. Please refer to the section on sync processing for more

information.

127

VSOUT

Digital

Output

Vertical Sync Output. A delayed version of the input vertical

synchronization signal. Please refer to the section on sync processing for

more information.

126

SOGOUT

Digital

Output

Sync-On-Green Output. A logic level signal that is the output of the

Sync-On-Green slicer circuit. Please refer to the section on sync

processing for more information.

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