ADCS9888 datasheet(22/34 Pages) NSC

22 / 34 page

Configuration Register Descriptions (Continued)

Address

(Hex)

Write/Read

or Read Only

Bits

POR Value

Name

Bit Name/Description

15H

W/R

1*******

Channel Mode

Sets the channel mode of the data outputs. 0 = single

channel mode. 1 = dual channel mode. In dual channel

mode, the DATACK output clocks operate at 1/2 of the

pixel conversion rate, and pixel data is updated on the

A and B output ports. See also Register 15H, bit 6.

*1******

Output Mode

Sets the output mode of the data outputs. 0 =

interleaved mode, 1 = parallel mode. In interleaved

mode, one output port is updated on the rising edge of

DATACK, the other output port is updated on the falling

edge of DATACK.

**0*****

A/B Even/Odd

When this bit is set to 1, HSOUT transitions on the

rising edge of DATACK. (Instead of the falling edge as

shown in the timing diagrams).

***0****

4:2:2 Output

Mode

Selects 4:2:2 subsampled output formatting mode, for

use with YUV type video signals. 0 = normal output

formatting, 1 = 4:2:2 output formatting.

In YUV 4:2:2 mode, the channel connections and data

output are as follows:

Channel

Input Signal

Output

Red

U/V

Green

Blue

High Z

****0***

Input Mux

Selects which video input source is used. 0 = port 0, 1

= port 1.

2:1

*****11*

Input

Bandwidth

Sets the analog input bandwidth.

11 = 500 MHz

10 = 300 MHz

01 = 150 MHz

00=75MHz

*******0

External Clock

Determines whether the internal Hsync referenced PLL

is used as the clock source, or the CKEXT source is

used. 0 = internal PLL. 1 = CKEXT is used.

16H

W/R

7:0

11111111

Test Register

17H

W/R

7:0

00000000

Test Register

18H

7:0

Test Register

19H

7:0

Test Register

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