ADCS9888 datasheet(4/34 Pages) NSC

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Pin Descriptions

Label

Type

Description

Analog Video Inputs

AIN0

Analog

Input

Channel 0 Red (V) Video Input. Input for Red component video channel or

V chrominance channel in YUV/YPbPr/YCbCr applications. A high

impedance analog input. Input signal should be capacitively coupled to the

input using a 0.1 µF capacitor to support clamping and DC restoration.

Signal range of 0.5 V

PP to 1.0 VPP depending on gain setting.

AIN0

Analog

Input

Channel 0 Green (Y) Video Input. Input for Green component video

channel or Y luminance channel in YUV/YPbPr/YCbCr applications. A high

impedance analog input. Input signal should be capacitively coupled to the

input using a 0.1 µF capacitor to support clamping and DC restoration.

Signal range of 0.5 V

PP to 1.0 VPP depending on gain setting.

AIN0

Analog

Input

Channel 0 Blue (U) Video Input. Input for Blue component video channel

or U chrominance channel in YUV/YPbPr/YCbCr applications. A high

impedance analog input. Input signal should be capacitively coupled to the

input using a 0.1 µF capacitor to support clamping and DC restoration.

Signal range of 0.5 V

PP to 1.0 VPP depending on gain setting.

AIN1

Analog

Input

Channel 1 Red (V) Video Input. See R

AIN0 for more information.

AIN1

Analog

Input

Channel 1 Green (Y) Video Input. See G

AIN0 for more information.

AIN1

Analog

Input

Channel 1 Blue (U) Video Input. See B

AIN0 for more information.

Analog Video Sync

SOGIN0

Analog

Input

Channel 0 Sync-On-Green-Input. A high impedance analog input. The

video channel containing synchronization information should be

capacitively coupled to this input using a 1.0 nF capacitor to support

negative peak clamping of the signal. When unused, this input should be

left unconnected.

SOGIN1

Analog

Input

Channel 1 Sync-On-Green-Input. See SOGIN0 for more information.

Sync/Clock Inputs

HSYNC0

Digital Input Channel 0 Horizontal Sync Input. A logic level synchronization signal at the

horizontal line rate is applied to this input. In applications where a

composite, logic level sync signal is present, that signal should be

connected to the HSYNC input. A Schmitt trigger input is used for

improved noise rejection. See the applications section for more

information.

VSYNC0

Digital Input Channel 0 Vertical Sync Input. A logic level synchronization signal at the

vertical frame rate is applied to this input. A Schmitt trigger input is used

for improved noise rejection. See the applications section for more

information.

HSYNC1

Digital Input Channel 1 Horizontal Sync Input. See HSYNC0 for more information.

VSYNC1

Digital Input Channel 1 Vertical Sync Input. See VSYNC0 for more information.

CLAMP

Digital Input External CLAMP Timing Input. When enabled via Register OFh, Bit 7, this

input will turn on the clamp circuits in the analog video inputs. This signal

should be asserted during the black reference portion of the video

waveform. Please refer to the applications section for more information.

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