3. Instruction Set

The 2-wire serial interface allows the user to communicate with the epc600 chip. The graph of the principle communication flow is in

Figure 13.

Starting a measurement, reading the result and setting the correct user parameters for operation are the main functions. All configurations

are set at run-time, are loaded immediately and are not stored in the chip.

3.1. 2-wire serial interface

The interface is for single slave use. It is targeted to operate up to a 10MHz clock frequency. Only 2 wires, one bidirectional data transmis -

sion SDATA and a clock line SCLK, are needed (refer to Figure 25). This allows the use of a tiny microprocessor as a controller for the

chip. Based on a handshake protocol the chip is either receiving or transmitting data during active clock cycles.

LED

NC3

LEDF

VREF

VDDIO

VDDHPX

VDDPX

VDDCP

VDDBS

XTAL1

XTAL2

GNDM

VDDT

SDATA

SCLK

HLLED/NC2

NC1

VDDPLL

VDDCORE

GNDLED

GNDPLL

GNDA

GND

VDD

epc600

GND

VDD

Microprocessor

VDD +8.5V

GND

GND

+5.0V

I/O1

I/O2

2-wire interface

R1

+5.0V

Figure 25: 2-wire interface wiring (Note: For details to R1 see section SDATA line)

3.1.1. SCLK line

SCLK is the serial clock signal. It is unidirectional and always driven by the microprocessor. It is switched between LOW and HIGH state.

The maximum 'HIGH' pulse length is not defined. The maximum 'LOW' pulse length must be < 1ms.

ERROR handling: A 'LOW' pulse > 1ms will reset the epc600 chip.

3.1.2. SDATA line

SDATA is the serial data line. It is used in a bidirectional way. It is switched between LOW and high-ohmic state.

Depending on the communication direction, it is either driven to LOW by the microprocessor or the epc600 chip (refer to Figure 25). A

“wired-OR” compatible I/O circuitry on either side is used to handle unexpected error situations. It avoids permanent damage of each party

in case they drive opposite logic values.

The microprocessor can achieve the Wired-OR connection by using programmable open-drain I/O pads, or writing a permanent logic LOW

to the output and switching the line between the high-ohmic and transparent modes. A pull-up resistor R1 to +5.0V will terminate the line to

logic HIGH during the high-ohmic state. If the rise time of the SDATA line is not fast enough, the user may either enable an embedded pull-

up resistor in the microprocessor or add on each side of the line, close to the pins, external resistors in parallel.

ERROR handling: If the epc600 device detects a communication error, it will pull the SDATA line permanently to LOW until the interface will

be reset.

The general waveform definition and timing are listed in Figure 26 and Table 8.

In the idle state, the SCLK and SDATA lines are in the high state (outputs are in tristate mode terminated with a pull-up resistor). The trans -

mission is always initiated with a start bit on the SDATA line: SDATA = low. This forces the microprocessor to clock the SCLK line with the

necessary number of cycles for sending or reading the data. The falling edge of the clock puts the data to the SDATA line. At the time of

the rising edge, the data is valid and readable. After the last rising clock edge the sender unlocks the SDATA line and both lines remain in

the high state.

© 2014 ESPROS Photonics Corporation

Characteristics subject to change without notice

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Datasheet epc600 - V1.3

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