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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA311B датащи(PDF) 42 Page - STMicroelectronics |
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STA311B датащи(HTML) 42 Page - STMicroelectronics |
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42 / 102 page  Registers STA311B 42/102 DocID024340 Rev 1 Setting the ZDE bit enables the zero-detect automatic mute. See Section 9.5.7 for more details. Setting the IDE bit enables this function, which looks at the input I²S data and will automatically mute if the signals are perceived as invalid. The BCLE bit detects loss of input MCLK in binary mode and will output 50% duty cycle. The LDTE bit actively prevents double triggering of LRCLK. When active, the ECLE bit will issue a device power-down signal (EAPD) on clock loss detection. 8.2.9 Configuration register I (0x08) Bit RW RST Name Description 2 RW 1 SVE Soft volume enable: 1: volume adjustments use soft volume 0: volume adjustments occur immediately Bit RW RST Name Description 3RW 1 ZDE Zero-detect mute enable: setting of 1 enables the automatic zero-detect mute Bit RW RST Name Description 4RW 1 IDE Invalid input detect mute enable: 1: enable the automatic invalid input detect mute Bit RW RST Name Description 5 RW 1 BCLE Binary output mode clock loss detection enable Bit RW RST Name Description 6 RW 1 LDTE LRCLK double trigger protection enable Bit RW RST Name Description 7 RW 0 ECLE Auto EAPD on clock loss D7 D6 D5 D4 D3 D2 D1 D0 EAPD PSCE 0 0 |
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