STM32L062T8 datasheet(87/118 Pages) STMICROELECTRONICS

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STM32L062x8

Electrical characteristics

Figure 27. 12-bit buffered/non-buffered DAC

tSETTLING

Settling time (full scale: for a

12-bit code transition between

the lowest and the highest

input codes till DAC_OUT

reaches final value ±1LSB

CL ≤ 50 pF, RL ≥ 5 kΩ

µs

Update rate

Max frequency for a correct

DAC_OUT change (95% of

final value) with 1 LSB

variation in the input code

CL ≤ 50 pF, RL ≥ 5 kΩ

Msps

tWAKEUP

Wakeup time from off state

(setting the ENx bit in the DAC

Control register)(9)

CL ≤ 50 pF, RL ≥ 5 kΩ

µs

PSRR+

VDDA supply rejection ratio

(static DC measurement)

CL ≤ 50 pF, RL ≥ 5 kΩ

--60

-35

1. Guaranteed by characterization results.

2. Guaranteed by design, not tested in production.

3. Connected between DAC_OUT and VSSA.

4. Difference between two consecutive codes - 1 LSB.

5. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

6. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.

7. Difference between the value measured at Code (0x001) and the ideal value.

8. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when

buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON.

9. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

Table 58. DAC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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