STM8S105C4 datasheet(47/121 Pages) STMICROELECTRONICS

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STM8S105x4/6

Option byte

0x487E

Bootloader

OPTBL

BL[7:0]

0x00

0x487F

NOPTBL

NBL[7:0]

0xFF

Table 11. Option byte (continued)

Addr.

Option

name

Option

byte

no.

Option bits

Factory

default

setting

765

Table 12. Option byte description

Option byte no.

Description

OPT0

ROP[7:0]

Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)

Note: Refer to the family reference manual (RM0016) section on

Flash/EEPROM memory readout protection for details.

OPT1

UBC[7:0]

User boot code area

0x00: no UBC, no write-protection

0x01: Page 0 to 1 defined as UBC, memory write-protected

0x02: Page 0 to 3 defined as UBC, memory write-protected

0x03: Page 0 to 4 defined as UBC, memory write-protected

...

0x3E: Pages 0 to 63 defined as UBC, memory write-protected

Other values: Reserved

Note: Refer to the family reference manual (RM0016) section on Flash write

protection for more details.

OPT2

AFR[7:0]

Refer to the following table for the description of the alternate function

remapping description of bits [7:2].

OPT3

HSITRIM:

High speed internal clock trimming register size

0: 3-bit trimming supported in CLK_HSITRIMR register

1: 4-bit trimming supported in CLK_HSITRIMR register

LSI_EN:

Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW:

Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

WWDG_HW:

Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT:

Window watchdog reset on halt

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active

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