ST7FOXA0 datasheet(61/123 Pages) STMICROELECTRONICS

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ST7FOXA0

On-chip peripherals

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The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the

reset. It is automatically cleared after it has been read.

Caution:

Once the WDGRF bit is set, if the watchdog is enabled, the microcontoller is immediatly

reset, even if the WDGD bit is set by software.

Hardware Watchdog Option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the

WDGE bit in the LTCSR is not used.

Refer to the Option Byte description in the "device configuration and ordering information"

section.

Using Halt Mode with the Watchdog (option)

If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be

used when the watchdog is enabled.

In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite

Timer stops counting and is no longer able to generate a Watchdog reset until the

microcontroller receives an external interrupt or a reset.

If an external interrupt is received, the WDG restarts counting after 256 or 512 CPU clocks.

If a reset is generated, the Watchdog is disabled (reset state).

If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT

instruction), it is recommended before executing the HALT instruction to refresh the WDG

counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

Figure 29.

Watchdog timing diagram

9.1.5

Input capture

The 8-bit input capture register is used to latch the free-running upcounter after a rising or

falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and

the LTICR register contains the MSB of the free-running upcounter. An interrupt is

generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.

An overflow can be detected through the timebase event. This overflow occurs when the

counter rolls over from 1F3Fh to 00h, that is, from F9h to 00h if only the 8 MSB of the LTIC

counter are taken into account. In this case, the TB bit in the LTCSR register must be reset

to detect all overflows.

The LTICR is a read only register and always contains the data from the last input capture.

Input capture is inhibited if the ICF bit is set.

tWDG

fWDG

INTERNAL

WATCHDOG

RESET

WDGD BIT

SOFTWARE SETS

WDGD BIT

HARDWARE CLEARS

WDGD BIT

WATCHDOG RESET

(2 ms @ 8 MHz fOSC)

Obsolete

Product(s)

- Obsolete

Product(s)

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