ST7FOXA0 datasheet(58/123 Pages) STMICROELECTRONICS

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I/O ports

ST7FOXA0

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8.6

Interrupts

The external interrupt event generates an interrupt if the corresponding configuration is

selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM

instruction).

See application notes AN1045 software implementation of I2C bus master, and AN1048 -

software LCD driver

8.7

Device-specific I/O port configuration

The I/O port register configurations are summarized in Table 18.

Table 18.

Port configuration

Table 19.

I/O port register map and reset values

Table 17.

Description of interrupt events

Interrupt Event

Event flag

Enable

Control bit

Exit from

Wait

Exit from

Halt

External interrupt on selected

external event

DDRx

ORx

Yes

Port

Pin name

Input (DDR=0)

Output (DDR=1)

OR = 0

OR = 1

OR = 0

OR = 1

Port A

PA0:2, PA4:5 (1)

IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in HALT and AWUFH modes. Refer

to 11.3.2: External Interrupt Control Register 2 (EICR2) on page 91.

floating

pull-up interrupt (1)

open drain

push-pull

PA3 (2)

After reset, to configure PA3 as a general purpose output, the application has to program the MUXCR0

and MUXCR1 registers. See Section 6.3.6: Multiplexed IO reset control register 1 (MUXCR1) on page 34

and Section 6.3.7: Multiplexed IO reset control register 0 (MUXCR0) on page 34

open drain

push-pull

Address

(Hex.)

Label

765

210

0000h

PADR

Reset

Value

MSB

000

LSB

0001h

PADDR

Reset

Value

MSB

000

LSB

0002h

PAOR

Reset

Value

MSB

000

LSB

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