TMS320VC5402 datasheet(10/72 Pages) TI1

10 / 72 page

TMS320VC5402

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTION

TYPE†

TERMINAL

NAME

DESCRIPTION

TYPE†

HOST-PORT INTERFACE SIGNALS

HD0−HD7

I/O/Z

Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the

HPI registers. These pins can also be used as general-purpose I/O pins. HD0−HD7 is placed in the

high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to

reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven

by the 5402, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled

at reset and can be enabled/disabled via the HBH bit of the BSCR.

HCNTL0

HCNTL1

Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have

internal pullup resistors that are only enabled when HPIENA = 0.

HBIL

Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup

resistor that is only enabled when HPIENA = 0.

HCS

Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input

has an internal pullup resistor that is only enabled when HPIENA = 0.

HDS1

HDS2

Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs

have internal pullup resistors that are only enabled when HPIENA = 0.

HAS

Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA

HR/W

Read/write. HR/W controls the direction of an HPI transfer. R/W has an internal pullup resistor that is only

enabled when HPIENA = 0.

HRDY

O/Z

Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the

high-impedance state when OFF is low.

HINT

O/Z

Host interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high

. HINT can

also be configured as the timer 1 output (TOUT1), when the HPI is disabled. The signal goes into the

high-impedance state when OFF is low.

HPIENA

HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor

is always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low

during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the 5402

is reset.

SUPPLY PNS

CVDD

+VDD. Dedicated 1.8-V power supply for the core CPU

DVDD

+VDD. Dedicated 3.3-V power supply for the I/O pins

VSS

Ground

TEST PINS

TCK

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes

on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction

on the falling edge of TCK.

TDI

IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK.

TDO

O/Z

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out

of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in

progress. TDO also goes into the high-impedance state when OFF is low.

TMS

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into

the TAP controller on the rising edge of TCK.

† I = input, O = output, Z = high impedance, S = supply

‡ All revisions of the 5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN

pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).

Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.

§ Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,

a buffer is recommended to ensure the VIL and VIH specifications are met.

TMS320VC5402 датащи(PDF) 10 Page - Texas Instruments

TMS320VC5402 датащи(HTML) 10 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

датащи скачать

ссылки URL