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TMS320VC5402 датащи(PDF) 53 Page - Texas Instruments |
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TMS320VC5402 датащи(HTML) 53 Page - Texas Instruments |
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53 / 72 page ![]() TMS320VC5402 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008 53 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings switching characteristics over recommended operating conditions for IAQ and IACK [H = 0.5 tc(CO)] (see Figure 25) PARAMETER MIN MAX UNIT td(CLKL-IAQL) Delay time, CLKOUT low to IAQ low −1 3 ns td(CLKL-IAQH) Delay time, CLKOUT low to IAQ high −1 3 ns td(A)IAQ Delay time, address valid to IAQ low 1 ns td(CLKL-IACKL) Delay time, CLKOUT low to IACK low −1 3 ns td(CLKL-IACKH) Delay time , CLKOUT low to IACK high −1 3 ns td(A)IACK Delay time, address valid to IACK low 3 ns th(A)IAQ Hold time, IAQ high after address invalid −2 ns th(A)IACK Hold time, IACK high after address invalid −2 ns tw(IAQL) Pulse duration, IAQ low 2H−2 ns tw(IACKL) Pulse duration, IACK low 2H−2 ns MSTRB IACK IAQ A[19:0] CLKOUT td(A)IACK td(A)IAQ tw(IACKL) th(A)IACK td(CLKL-IACKL) tw(IAQL) th(A)IAQ td(CLKL-IAQL) td(CLKL-IACKH) td(CLKL-IAQH) Figure 25. IAQ and IACK Timings |
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