TMS320VC5402 datasheet(9/72 Pages) TI1

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TMS320VC5402

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTION

TYPE†

TERMINAL

NAME

DESCRIPTION

TYPE†

MEMORY CONTROL SIGNALS (CONTINUED)

MSC

O/Z

Microstate complete. MSC indicates completion of all software wait states. When two or more software wait

states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive

high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external

wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF

is low.

IAQ

O/Z

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address

bus. IAQ goes into the high-impedance state when OFF is low.

OSCILLATOR/TIMER SIGNALS

CLKOUT

O/Z

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle

is bounded by rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low.

CLKMD1

CLKMD2

CLKMD3

Clock mode select signals. These inputs select the mode that the clock generator is initialized to after reset. The

logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized

to the selected mode. After reset, the clock mode can be changed through software, but the clock mode select

signals have no effect until the device is reset again.

X2/CLKIN

Oscillator input. This is the input to the on-chip oscillator.

If the internal oscillator is not used, X2/CLKIN functions as the clock input, and can be driven by an external clock

source.‡

Output pin from the internal oscillator for the crystal.

If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state

when OFF is low.‡

TOUT0

O/Z

Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT

cycle wide. TOUT0 also goes into the high-impedance state when OFF is low.

TOUT1

O/Z

Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is one

CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI and is only available when

the HPI is disabled. TOUT1 also goes into the high-impedance state when OFF is low.

MULTICHANNEL BUFFERED SERIAL PORT SIGNALS

BCLKR0

BCLKR1

I/O/Z

Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following

reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.

BDR0

BDR1

Serial data receive input

BFSR0

BFSR1

I/O/Z

Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured

as an input following reset. The BFSR pulse initiates the receive data process over BDR.

BCLKX0

BCLKX1

I/O/Z

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as

an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when

OFF goes low.

BDX0

BDX1

O/Z

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is

asserted, or when OFF is low.

BFSX0

BFSX1

I/O/Z

Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX

can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the

high-impedance state when OFF is low.

MISCELLANEOUS SIGNAL

No connection

† I = input, O = output, Z = high impedance, S = supply

‡ All revisions of the 5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN

pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).

Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.

§ Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,

a buffer is recommended to ensure the VIL and VIH specifications are met.

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