TMS320VC5402 datasheet(27/72 Pages) TI1

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TMS320VC5402

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

memory-mapped registers

The 5402 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h to

1Fh. Table 9 gives a list of CPU memory-mapped registers (MMRs) available on 5402. The device also has a

set of memory-mapped registers associated with peripherals. Table 10, Table 11, and Table 12 show additional

peripheral MMRs associated with the 5402.

Table 9. CPU Memory-Mapped Registers

NAME

ADDRESS

DESCRIPTION

NAME

DEC

HEX

DESCRIPTION

IMR

Interrupt mask register

IFR

Interrupt flag register

–

2−5

Reserved for testing

ST0

Status register 0

ST1

Status register 1

Accumulator A low word (15−0)

Accumulator A high word (31−16)

Accumulator A guard bits (39−32)

Accumulator B low word (15−0)

Accumulator B high word (31−16)

Accumulator B guard bits (39−32)

TREG

Temporary register

TRN

Transition register

AR0

Auxiliary register 0

AR1

Auxiliary register 1

AR2

Auxiliary register 2

AR3

Auxiliary register 3

AR4

Auxiliary register 4

AR5

Auxiliary register 5

AR6

Auxiliary register 6

AR7

Auxiliary register 7

Stack pointer register

Circular buffer size register

BRC

Block repeat counter

RSA

Block repeat start address

REA

Block repeat end address

PMST

Processor mode status (PMST) register

XPC

Extended program page register

–

Reserved

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