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Analog to Digital Converter (ADC)

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16.0 Analog to Digital Converter (ADC)

The ADC receives analog signals on eight channels (AD0-

7). It converts these signals to their digital representation

and stores the results in four byte-wide registers.

16.1 FEATURES

• 8-bit resolution

• 8 input channels

• Input voltage range from zero to V

REF

• Internal or external reference voltage

• Timing specifications:

— 10 ADC-clock cycles conversion time

— Up to 1 MHz ADC clock

— Programmable sampling time to guarantee input

settling time

• Flexible conversion modes:

— Single or continuous conversion

— Single channel or four channel scanning

• Polling or interrupt driven operation

• Zero current consumption when disabled, low current

when enabled

• High impedance inputs

16.2 FUNCTIONAL DESCRIPTION

The ADC has eight analog inputs, AD0-7, as shown in Fig-

ure 16-1. The analog multiplexer selects one of them and

connects it to Sample and Hold. The input signal is sampled

before the conversion begins.

Sample and Hold charges the CS capacitor during the sam-

pling time, and holds the voltage value on this capacitor dur-

ing the conversion period. Programmable sampling time

allows the voltage on the sampling capacitor to settle before

being latched.

The ADC is implemented by a single, 8-bit, successive ap-

proximation digital to analog converter (DAC). The output of

the DAC is compared with the sampled value by the Com-

parator (Comp).

ADC Control Logic performs a 10 clock cycle successive

approximation algorithm to find the digital representation of

the input signal.

Configuration (Config) automates ADC operation. Four op-

erational modes allow the ADC to convert one or four of the

input signals, in single or repetitive (scan) modes.

The ADC interfaces through the four status and control reg-

isters with the peripheral bus. the four data output buffers

also interface with the same bus, and can store up to four

conversion results.

The Clock Divider reduces the frequency of the system

clock to the lower value required by the ADC. The on-chip

VREF source can be enabled and connected internally to the

DAC reference input.

Peripheral

ADCCLK

Figure 16-1. ADC Functional Diagram

DAC

Comp

ADC

Sample

8:1

Analog

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

MUX

0.47

AVCC

VREF

AGND

AVCC

0.1

AVCC

ADC

Data

Buffers

Clock

Divider

System

Clock

Bus

PC87570

Reset

Analog

Power

µF

3.3 V

5.0 V

AVCC

to other

modules

µF

Config

Int

Ref

and Hold

AD7

VIN0

AD0

Control Logic

VIN7

Status

and Control

Registers

INTREF

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