PC87332VLJ datasheet(29/98 Pages) NSC

29 / 98 page

30 FDC Register Description (Continued)

Write Data

Active high status of latched WDATA

signal This bit is latched by the inactive going edge

of WDATA and is cleared by a read from the DIR

This bit is not gated by WGATE

Read Data

Active high status of latched RDATA

signal It is latched by the inactive going edge of

RDATA and is cleared by a read from the DIR

Write Gate

Active high status of latched WGATE

signal This bit is latched by the active going edge of

WGATE and is cleared by a read from the DIR

Drive Select 3

Active low status of the DR3 disk

interface output

Note

The MTR3 MTR2 DRV3 DRV2 pins are only available in

four drive mode (bit 4 of FER is 1) and require external logic

Drive Select 2

Active low status of the DR2 disk

interface output

Note

The MTR3 MTR2 DRV3 DRV2 pins are only available in

four drive mode (bit 4 of FER is 1) and require external logic

313 Digital Output Register (DOR)

ReadWrite

The DOR controls the drive select and motor enable disk

interface outputs enables the DMA logic and contains a

software reset bit The contents of the DOR are set to 00h

after a hardware reset and is unaffected by a software re-

set The DOR can be written to at any time

DOR

DESC

MTR3 MTR2 MTR1 MTR0 DMAEN RESET

DRIVE DRIVE

SEL 1

SEL 0

RESET

0000

COND

Motor Enable 3

This bit controls the MTR3 disk

interface output A 1 in this bit causes the MTR3 pin

to go active

Motor Enable 2

Same function as D7 except for

MTR2

Motor Enable 1

Same function as D7 except for

MTR1 (See bit 4 of FCR for further information)

Motor Enable 0

Same function as D7 except for

MTR0 (See bit 4 of FCR for further information)

DMA Enable

This bit has two modes of operation

PC-AT mode or Model 30 mode Writinga1to this

bit enables the DRQ DACK TC and IRQ6 pins

Writinga0to this bit disables the DACK and TC pins

and puts the DRQ and the IRQ6 pins in TRI-STATE

D3 is a 0 after a reset when in these modes

PS2 mode This bit is reserved and the DRQ

DACK TC and IRQ6 pins are always enabled Dur-

ing a reset the DRQ DACK TC and IRQ6 lines

remain enabled and D3 is 0

Reset Controller

Writinga0to this bit resets the

controller It remains in the reset condition until a 1

is written to this bit A software reset does not affect

the DSR CCR and other bits of the DOR A soft-

ware reset affects the Configure and Mode com-

mand bits (See Section 40 FDC Command Set De-

scription) The minimum time that this bit must be

low is 100 ns Thus toggling the Reset Controller bit

during consecutive writes to the DOR is an accept-

able method of issuing a software reset

D1D0 Drive Select

These two bits are binary encoded for

the four drive selects DR0 – DR3 so that only one

drive select output is active at a time (See bit 4 of

FCR for further information)

It is common programming practice to enable both the mo-

tor enable and drive select outputs for a particular drive

Table 3-2 below shows the DOR values which enable each

of the four drives

TABLE 3-2 Drive Enable Values

Drive

DOR Value

1Ch

2Dh

4Eh

8Fh

Note

The MTR3 MTR2 DRV3 DRV2 pins are only available in four drive

mode (bit 4 of FER is 1) and require external logic

314 Tape Drive Register (TDR)

ReadWrite

This register is used to assign a particular drive number to

the tape drive support mode of the data separator All other

logical drives can be assigned as floppy drive support Any

future reference to the assigned tape drive invokes tape

drive support The TDR is unaffected by a software reset

This register holds the media sense information of the flop-

py disk drive When bit 0 of FCR is 1 bits 2 – 7 of TDR are

TRI-STATE during read

TDR

DESC

Valid

XXX

TAPE

Data

SEL 1

SEL 0

RESET

COND

Extra Density

When bit 5 is 0 this media ID bit is

used with bit 6 to indicate the type of media currently

in the active floppy drive If bit 5 is 1 it is invalid This

bit holds MSEN1 pin value When PPM is enabled

and PNF is 0 it holds the PD7 pin value See Table

3-3 for details regarding bits 5 – 7

High Density

When bit 5 is 0 this media ID bit is

used with bit 7 to indicate the type of media currently

in the active floppy drive If bit 5 is 1 it is invalid This

bit holds MSEN0DRATE0 pin value When PPM is

enabled and PNF is 0 it holds the PD5 pin value

See Table 3-3 for details regarding bits 5 – 7

Note

Bits 6 and 7 of TDR are undefined when DRID01 pins are

configured as DRATE01

Valid Data

The state of bit 5 is determined by the

state of the VLD01 pins during reset If this bit is 0

there is valid media ID sense data in bits 7 and 6 of

this register Bit 5 holds VLD0 when drive 0 is ac-

cessed and media sense is configured It holds

VLD1 when drive 1 is accessed and media sense is

configured Otherwise it is set to 1 to indicate that

media information is not available See Table 3-3 for

details regarding bits 5 – 7

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