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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PC87332VLJ датащи(PDF) 28 Page - National Semiconductor (TI) |
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PC87332VLJ датащи(HTML) 28 Page - National Semiconductor (TI) |
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28 / 98 page  30 FDC Register Description (Continued) TABLE 3-1 Register Description and Addresses A2 A1 A0 IDENT RW Register 0 0 0 0 R Status Register A SRA 0 0 1 0 R Status Register B SRB 0 1 0 X RW Digital Output Register DOR 0 1 1 X RW Tape Drive Register TDR 1 0 0 X R Main Status Register MSR 1 0 0 X W Data Rate Select Register DSR 1 0 1 X RW Data Register (FIFO) FIFO 1 1 0 X X None (Bus TRI-STATE) 1 1 1 X R Digital Input Register DIR 1 1 1 X W Configuration Control Register CCR Note SRA and SRB are enabled by IDENT e 0 during a chip reset only 311 Status Register A (SRA) Read Only This read-only diagnostic register is part of the PS2 floppy controller register set and is enabled when in the PS2 or Model 30 mode This register monitors the state of the IRQ6 pin and some of the disk interface signals The SRA can be read at any time when in PS2 mode In the PC-AT mode D7 – D0 are TRI-STATE during a mP read SRAPS2 Mode D7 D6 D5 D4 D3 D2 D1 D0 DESC IRQ6 DRV2 STEP TRK0 HDSEL INDX WP DIR PEND RESET 0 NA 0 NA 0 NA NA 0 COND D7 Interrupt Pending This active high bit reflects the state of the IRQ6 pin D6 2nd Drive Installed Active low status of the DRV2 disk interface input indicating if a second drive has been installed D5 Step Active high status of the STEP disk interface output D4 Track 0 Active low status of the TRK0 disk inter- face input D3 Head Select Active high status of the HDSEL disk interface output D2 Index Active low status of the INDEX disk interface input D1 Write Protect Active low status of the WP disk in- terface input D0 Direction Active high status of the DIR disk inter- face output SRA Model 30 Mode D7 D6 D5 D4 D3 D2 D1 D0 DESC IRQ6 DRQ STEP TRK0 HDSEL INDX WP DIR PEND RESET 0 0 0 NA 1 NA NA 1 COND D7 Interrupt Pending This active high bit reflects that state of the IRQ6 pin D6 DMA Request Active high status of the DRQ signal D5 Step Active high status of the latched STEP disk interface output This bit is latched with the STEP output going active and is cleared with a read from the DIR or with a hardware or software reset D4 Track 0 Active high status of TRK0 disk interface input D3 Head Select Active low status of the HDSEL disk interface output D2 Index Active high status of the INDEX disk inter- face input D1 Write Protect Active high status of the WP disk interface input D0 Direction Active low status of the DIR disk inter- face output 312 Status Register B (SRB) Read Only This read-only diagnostic register is part of the PS2 floppy controller register set and is enabled when in the PS2 or Model 30 mode The SRB can be read at any time when in PS2 mode In the PC-AT mode D7 – D0 are TRI-STATE during a mP read SRBPS2 Mode D7 D6 D5 D4 D3 D2 D1 D0 DESC 1 1 DR0 WDATA RDATA WGATE MTR1 MTR0 RESET NA NA 0 0 0 0 0 0 COND D7 Reserved Always 1 D6 Reserved Always 1 D5 Drive Select 0 Reflects the status of the Drive Se- lect 0 bit in the DOR (address 2 bit 0) It is cleared after a hardware reset not a software reset D4 Write Data Every inactive edge transition of the WDATA disk interface output causes this bit to change states D3 Read Data Every inactive edge transition of the RDATA disk interface output causes this bit to change states D2 Write Gate Active high status of the WGATE disk interface output D1 Motor Enable 1 Active high status of the MTR1 disk interface output Low after a hardware reset unaffected by a software reset D0 Motor Enable 0 Active high status of the MTR0 disk interface output Low after a hardware reset unaffected by a software reset SRBModel 30 Mode D7 D6 D5 D4 D3 D2 D1 D0 DESC DRV2 DR1 DR0 WDATA RDATA WGATE DR3 DR2 RESET NA 1 1 0 0 0 1 1 COND D7 2nd Drive Installed Active low status of the DRV2 disk interface input D6 Drive Select 1 Active low status of the DR1 disk interface output D5 Drive Select 0 Active low status of the DR0 disk interface output 28 |
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