PC87309VLJ datasheet(155/192 Pages) NSC

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Power Management (Logical Device 4)

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7.0

Power Management

(Logical Device 4)

7.1

POWER MANAGEMENT OPTIONS

The Power Management logical device provides configura-

tion options. Registers in this logical device enable activa-

tion of other logical devices, and set signal characteristics

for certain I/O pins. (See Section 7.2 "THE POWER MAN-

AGEMENT REGISTERS".)

7.2

THE POWER MANAGEMENT REGISTERS

Seventeen Power Management register control, activate

and monitor all activity of the power Management Logical

device.

Access to these registers is achieved by the use of two reg-

isters mapped in the PC87309 address space. The Power

Management registers are accessed via the Power Man-

agement Index and Data registers, which are located at

base address and base address + 01h, respectively. The

base address is indicated by the Base Address registers at

indexes 60h and 61h of Logical Device 4, respectively. See

TABLE 2-15 "Power Management Configuration Registers

- Logical Device 4" on page 27. TABLE 7-1 "The Power

Management Registers" lists these registers.

TABLE 7-1. The Power Management Registers

7.2.1

Power Management Index Register

This read/write register points to one of the Power Manage-

ment registers. Bits 7 through 3 are read only and return

00000 when read.

It is reset by hardware to 00h. The data in the indicated reg-

ister is accessed via the Power Management Data register

at the base address + 01h.

7.2.2

Power Management Data Register

This read/write register contains the data in the register

pointed to by the Power Management Index register at the

base address.

7.2.3

Function Enable Register 1 (FER1)

The bits of this register enable or disable activity of Logic

devices within the PC87309.

A set bit enables activation of the corresponding logical de-

vice via its Active register at index 30h.

A cleared bit disables the corresponding logical device re-

gardless of the value in its Active register. Bit 0 of the Active

ing FER1 bit is cleared.

Hard reset sets this read/write register to FFh.

Bit 0 - KBC Function Enable

0: Disabled.

1: Enabled. (Default)

Bit 1 - Reserved

Bit 2 - Reserved

Bit 3 - FDC Function Enable

0: Disabled.

1: Enabled. (Default)

Bit 4 - Parallel Port Function Enable

0: Disabled.

1: Enabled. (Default).

Bit 5 - UART2 and Infrared Function Enable

0: Disabled.

Index Symbol

Description

Type

Base+0

Power Management Index Register R/W

Base+1

Power Management Data Register R/W

00h

FER1

Function Enable Register 1

R/W

01h

Reserved

02h

PMC1

Power Management Control 1

R/W

03h

Reserved

04h

PMC3

Power Management Control 3

R/W

05h-

07h

Reserved

Index of a Power

Read Only

76543210

Reset

Required

Base Address

Power Management

Management Register

Index Register,

+00h

Data in the Indicated Power

76543210

Reset

Required

Base Address

Power Management

Management Register

Data Register,

+ 01h

KBC Function Enable

76543210

Reset

Required

Index 00h

Function Enable

UART2 and Infrared Function Enable

FDC Function Enable

Parallel Port Function Enable

UART1 Function Enable

Reserved

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