PC87309VLJ datasheet(156/192 Pages) NSC

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Power Management (Logical Device 4)

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1: Enabled. (Default).

Bit 6 - UART1 Function Enable

0: Disabled.

1: Enabled. (Default).

Bit 7 - Reserved

7.2.4

Power Management Control Register (PMC1)

The bits of this register place the signals of the correspond-

ing inactive logical device in TRI-STATE (except IRQ and

DMA pins) when set to “1”,regardless of the value of bit 0 of

the corresponding logical device register at index F0h.

A cleared bit has no effect. In this case, the TRI-STATE sta-

tus of signals is controlled by bit 0 of the corresponding log-

ical device register at index F0h.

This is an OR function between PMC1 and the register at in-

dex F0h of the corresponding logical device.

Hard reset clears this read/write register to 00h.

Bits 2-0 - Reserved

Bit 3 - FDC TRI-STATE Control

0: No effect. TRI-STATE controlled by bit 0 of the Su-

perI/O FDC Conﬁguration register. (Default)

See Section 2.5.1 "SuperI/O FDC Conﬁguration

1: FDC signals are in TRI-STATE.

Bit 4 - Parallel Port TRI-STATE Control

0: No effect. TRI-STATE controlled by bit 0 of the Su-

perI/O Parallel Port Conﬁguration register. (Default)

See Section 2.6 "SUPERI/O PARALLEL PORT

CONFIGURATION REGISTER (LOGICAL DEVICE

1)" on page 30.

1: Parallel Port signals are in TRI-STATE.

Bit 5 - UART2 and Infrared TRI-STATE Control

0: No effect. TRI-STATE controlled by bit 0 of the Su-

perI/O UART2 Conﬁguration register. (Default)

See “Bit 0 - TRI-STATE Control for UART2 signals”

on page 31.

1: UART2 signals are in TRI-STATE.

Bit 6 - UART1 TRI-STATE Control

0: No effect. TRI-STATE controlled by bit 0 of the Su-

perI/O UART1 Conﬁguration register. (Default)

See Section 2.8 "SUPERI/O UART1 CONFIGURA-

TION REGISTER (LOGICAL DEVICE 3)" on page 32.

1: UART1 signals are in TRI-STATE.

Bit 7 - Reserved

Reserved.

7.2.5

Power Management Control 3 Register (PMC3)

This register enables and monitors functions and devices.

Hard reset initializes this register to 0Eh.

Bit 0 - Power Management Timer CLock Enable

0: The clock is disabled.

The PM Timer registers (see Fixed ACPI registers)

are not accessible. Reads are ignored.

The TMR_STS and the TMR_EN bits (in PM1

Event registers) are read-only bits. Read returns 0.

1: The clock is enabled.

The PM Timer registers (see Fixed ACPI registers)

are accessible.

The TMR_STS and the TMR_EN bits (in PM1

Event registers) are functional.

Bit 1 - Parallel Port Clock Enable

This bit is ANDed with bit 1 of the SuperI/O Parallel Port

Configuration register at index F0h of Logical Device 4.

If either bit is cleared to 0, the clock is disabled. Both bits

must be set to 1 to enable the clock.

0: The clock is disabled.

1: If bit 1 of the SuperI/O Parallel Port Conﬁguration

Bit 2 - UART2 Clock Enable

This bit is ANDed with bit 1 of the SuperI/O UART2 Con-

figuration register at index F0h of Logical Device 2. If ei-

ther bit is cleared to 0, the clock is disabled. Both bits

must be set to 1 to enable the clock.

0: The clock is disabled.

1: If bit 1 of the SuperI/O UART2 Conﬁguration regis-

ter is set to 1, the clock is enabled. (Default)

FDC TRI-STATE Control

76543210

Reset

Required

Index 02h

Power Management

Control 1 Register

Parallel Port TRI-STATE Control

UART2 and Infrared TRI-STATE Control

Reserved

UART1 TRI-STATE Control

(PMC1)

UART1 Clock Enable

76543210

Reset

Required

Index 04h

Power Management

Control 3 Register

Reserved

UART1 Busy Indicator

UART2 Busy Indicator

UART2 Clock Enable

Parallel Port Clock Enable

(PMC3)

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