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PC87309VLJ датащи(PDF) 151 Page - National Semiconductor (TI) |
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PC87309VLJ датащи(HTML) 151 Page - National Semiconductor (TI) |
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151 / 192 page ![]() Enhanced Serial Port - UART1 (Logical Device 3) 151 www.national.com 6.8.1 Module Revision ID Register (MRID) This read-only register identifies the revision of the module. When read, it returns the module ID and revision level. This module returns the code 2xh, where x indicates the revision number. Bits 3-0 - Revision ID (MID3-0) The value in these bits identifies the revision level. Bits 7-4 - Module ID (MID7-4) The value in these bits identifies the module type. 6.8.2 Shadow of Line Control Register (SH_LCR) This register returns the value of the LCR register. The LCR register is written into when a byte value according to Table 6-8 on page 143, is written to the LCR/BSR registers loca- tion (at offset 03h) from any bank. See “Line Control Register (LCR)” on page 142 for bit de- scriptions. 6.8.3 Shadow of FIFO Control Register (SH_FCR) This read-only register returns the contents of the FCR reg- ister in bank 0. See “FIFO Control Register (FCR)” on page 142 for bit de- scriptions. 6.8.4 Line Control Register (LCR) and Bank Select Register (BSR) These registers are the same as the registers at offset 03h in bank 0. 6.9 UART1 REGISTER BITMAPS 76543210 Reset Required x x x x 0 1 0 0 Module Revision ID (MRID) Bank 3, Offset 00h Register Revision ID(RID 3-0) Module ID(MID 7-4) 76543210 Reset Required 0 0 0 0 0 0 0 0 Line Control Register (SH_LCR) Bank 3, Shadow of STB EPS STKP SBRK BKSE WLS0 WLS1 PEN Offset 01h 76543210 Reset Required 0 0 0 0 0 0 0 0 FIFO Control Register (SH_FCR) Bank 3, Shadow of TXSR TXFTH0 TXFHT1 RXFTH0 RXFTH1 FIFO_EN RXSR Reserved Offset 02h 76543210 Reset Required Receiver Data Register (RXD) Bank 0, Received Data Read Cycles Offset 00h 76543210 Reset Required Transmitter Data Register (TXD) Bank 0, Transmitted Data Write Cycles Offset 00h |
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