PC87309VLJ datasheet(149/192 Pages) NSC

149 / 192 page

Enhanced Serial Port - UART1 (Logical Device 3)

149

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6.7.2

Extended Control Register 1 (EXCR1)

Use this register to control module operation in the Extend-

ed mode. Upon reset all bits are set to 0.

Bit 0 - Extended Mode Select (EXT_SL)

When set to 1, the Extended mode is selected.

Bits 3 - 1 - Reserved

Read/Write 0.

Bit 4 - Loopback Enable (LOOP)

During loopback, the transmitter output is connected in-

ternally to the receiver input, to enable system self-test

of serial communications. In addition to the data signal,

all additional signals within the UART are interconnect-

ed to enable real transmission and reception using the

UART mechanisms.

When this bit is set to 1, loopback is selected. This bit

accesses the same internal register as bit 4 in the MCR

Loopback behaves similarly in both Non-Extended and

Extended modes.

When Extended mode is selected, the DTR bit in the

MCR register internally drives both DSR and RI, and the

RTS bit drives CTS and DCD.

During loopback, the following actions occur:

1. The transmitter and receiver interrupts are fully op-

erational. The Modem Status Interrupts are also fully

operational, but the interrupt sources are now the

lower bits of the MCR register.

2. UART and infrared receiver serial input signals are

disconnected. The internal receiver input signals are

connected to the corresponding internal transmitter

output signals.

3. The UART transmitter serial output is forced high

and the infrared transmitter serial output is forced

low, unless the ETDLBK bit is set to 1. In which case

they function normally.

4. The modem status input pins (DSR, CTS, RI and

DCD) are disconnected. The internal modem status

signals, are driven by the lower bits of the MCR reg-

ister.

Bit 5 - Enable Transmitter During Loopback (ETDLBK)

When this bit is set to 1, the transmitter serial output is

enabled and functions normally when loopback is en-

abled.

Bit 6 - Reserved

Read/Write 0.

Bit 7 - Baud Generator Test (BTEST)

When set to 1, this bit routes the Baud Generator to the

DTR pin for testing purposes.

6.7.3

Line Control Register (LCR) and Bank Select

These registers are the same as the registers at offset 03h

in bank 0.

6.7.4

Extended Control and Status Register 2

(EXCR2)

This register configures the Prescaler and controls the

Baud Divisor Register Lock.

Upon reset all bits are set to 0.

Bits 3 - 0 - Reserved

Read/Write 0.

Bits 5,4 - Prescaler Select

The prescaler divides the 24 MHz input clock frequency

to provide the clock for the Baud Generator. (See Table

6-13).

76543210

Reset

Required

High Byte Port

(BGD(H))

Bank 2,

Most Significant Byte

of Baud Generator

Baud Generator Divisor

Offset 01h

76543210

Reset

Required

Status Register 1

(EXCR1)

Bank 2,

Extended Control and

LOOP

ETDLBK

Reserved

BTEST

EXT_SL

Offset 02h

Reserved

76543210

Reset

Required

Status Register 2

(EXCR2)

Bank 2,

Extended Control and

PRESL0

PRESL1

Reserved

LOCK

Offset 04h

Reserved

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