PC87309VLJ datasheet(146/192 Pages) NSC

146 / 192 page

Enhanced Serial Port - UART1 (Logical Device 3)

146

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In the reset state, bits 4 through 7 are indeterminate as they

reflect their corresponding input signals.

Note: The modem status lines can be used as general

purpose inputs. They have no effect on the trans-

mitter or receiver operation.

Bit 0 - Delta Clear to Send (DCTS)

Set to 1, when the CTS input signal changes state.

This bit is cleared upon read.

Bit 1 - Delta Data Set Ready (DDSR)

Set to 1, when the DSR input signal changes state.

This bit is cleared upon read

Bit 2 - Trailing Edge Ring Indicate (TERI)

Set to 1, when the RI input signal changes state from

low to high.

This bit is cleared upon read

Bit 3 - Delta Data Carrier Detect (DDCD)

Set to 1, when the DCD input signal changes state.

1: DCD signal state changed.

Bit 4 - Clear To Send (CTS)

This bit returns the inverse of the CTS input signal.

Bit 5 - Data Set Ready (DSR)

This bit returns the inverse of the DSR input signal.

Bit 6 - Ring Indicate (RI)

This bit returns the inverse of the RI input signal.

Bit 7 - Data Carrier Detect (DCD)

This bit returns the inverse of the DCD input signal.

6.5.10

Scratchpad Register (SPR)

This register shares a common address with the ASCR

In Non-Extended mode, this is a scratch register (as in the

16550) for temporary data storage.

6.5.11

Auxiliary Status and Control Register (ASCR)

This register shares a common address with the previous

one (SCR).

This register is accessed when the Extended mode of op-

eration is selected. The definition of the bits in this case is

dependent upon the mode selected in the MCR register,

bits 7 through 5. This register is cleared upon hardware re-

set Bits 2 and 6 are cleared when the transmitter is “soft re-

set”. Bits 0,1,4 and 5 are cleared when the receiver is “soft

reset”.

Bit 0 - RX_FIFO Time-Out (RXF_TOUT)

This bit is read only and set to 1 when an RX_FIFO tim-

eout occurs. It is cleared when a character is read from

the RX_FIFO.

Bits 7 - 1 -Reserved

Read/Write 0.

6.6

BANK 1 – THE LEGACY BAUD GENERATOR

DIVISOR PORTS

This register bank contains two registers as the Baud Gen-

erator Divisor Port, and a bank select register.

The Legacy Baud Generator Divisor (LBGD) port provides

an alternate path to the Baud Divisor Generator register.

This bank is implemented to maintain compatibility with

16550 standard and to support existing legacy software

packages. In case of using legacy software, the addresses

0 and 1 are shared with the data ports RXD/TXD (see page

138). The selection between them is controlled by the value

of the BKSE bit (LCR bit 7 page 142).

76543210

Reset

Required

Modem Status

Bank 0,

TERI

CTS

DSR

DCD

DCTS

DDSR

DDCD

Offset 06h

76543210

Reset

Required

Scratchpad Register

(SCR)

Bank 0,

Scratch Data

Non-Extended Modes

Offset 07h

76543210

Reset

Required

Auxiliary Status

Bank 0,

RXF_TOUT

Extended Modes

Reserved

Offset 07h

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