PC87309VLJ datasheet(147/192 Pages) NSC

147 / 192 page

Enhanced Serial Port - UART1 (Logical Device 3)

147

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TABLE 6-9. Bank 1 Register Set

In addition, a fallback mechanism maintains this compatibil-

ity by forcing the UART to revert to 16550 mode if 16550

software addresses the module after a different mode was

set. Since setting the baud rate divisor values is a neces-

sary initialization of the 16550, setting the divisor values in

bank 1 forces the UART to enter 16550 mode. (This is

called fallback.)

To enable other modes to program their desired baud rates

without activating this fallback mechanism, the baud rate di-

visor register in bank 2 should be used.

6.6.1

Legacy Baud Generator Divisor Ports (LBGD(L)

and LBGD(H)),

The programmable baud rates in the Non-Extended mode

are achieved by dividing a 24 MHz clock by a prescale value

of 13, 1.625 or 1. This prescale value is selected by the

PRESL field of EXCR2 (see page 149). This clock is subdi-

vided by the two baud rate generator divisor buffers, which

output a clock at 16 times the desired baud rate (this clock is

the BOUT clock). This clock is used by I/O circuitry, and after

a last division by 16 produces the output baud rate.

Divisor values between 1 and 216-1 can be used. (Zero is

forbidden). The baud rate generator divisor must be loaded

during initialization to ensure proper operation of the baud

rate generator. Upon loading either part of it, the baud rate

generator counter is immediately loaded. Table 6-12 on

page 148 shows typical baud divisors. After reset the divisor

Any access to the LBGD(L) or LBGD(H) ports causes a re-

set to the default Non-Extended mode, i.e., 16550 mode

(See “AUTOMATIC FALLBACK TO A NON-EXTENDED

UART MODE” on page 138).To access a Baud Generator

Divisor when in the Extended mode, use the port pair in

bank 2 (BGD on page 148).

Table 6-10 shows the bits which are cleared when Fallback

occurs during Extended or Non-Extended modes.

If the UART is in Non-Extended mode and the LOCK bit is

1, the content of the divisor (BGD) ports will not be affected

and no other action is taken.

When programming the baud rate, the new divisor is loaded

upon writing into LBGD(L) and LBGD(H). After reset, the

contents of these registers are indeterminate.

Divisor values between 1 and 216-1 can be used. (Zero is

forbidden.) Table 6-12 shows typical baud rate divisors.

TABLE 6-10. Bits Cleared On Fallback

6.6.2

Line Control Register (LCR) and Bank Select

These registers are the same as the registers at offset 03h

in bank 0.

Offset

Name

Description

00h

LBGD(L)

Legacy Baud Generator

Divisor Port (Low Byte)

01h

LBGD(H)

Legacy Baud Generator

Divisor Port (High Byte)

02h

Reserved

03h

LCR/

BSR

Line Control /

Bank Select Register

04h - 07h

Reserved

UART Mode & LOCK bit before Fallback

Extended

Mode

LOCK = x

Non-Extended

Mode

LOCK = 0

Non-Extended

Mode

LOCK = 1

MCR

2 to 7

none

EXCR1

0, 5 and 7

5 and 7

none

EXCR2

0 to 5

none

76543210

Reset

Required

Low Byte port

(LBGD(L))

Bank 1,

Least Significant Byte

Legacy Baud Generator Divisor

of Baud Generator

Offset 00h

76543210

Reset

Required

High Byte port

(LBGD(H))

Bank 1,

Most Significant Byte

Legacy Baud Generator Divisor

of Baud Generator

Offset 01h

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