PC87309VLJ datasheet(145/192 Pages) NSC

145 / 192 page

Enhanced Serial Port - UART1 (Logical Device 3)

145

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Bits 4 through 1 of the LSR are the error conditions that gen-

erate a Receiver Line Status interrupt whenever any of the

corresponding conditions are detected and that interrupt is

enabled.

The LSR is intended for read operations only. Writing to the

LSR is not permitted

Bit 0 - Receiver Data Available (RXDA)

Set to 1 when the Receiver Holding Register is full.

If the FIFOs are enabled, this bit is set when at least one

character is in the RX_FIFO.

Cleared when the CPU reads all the data in the Holding

Bit 1 - Overrun Error (OE)

This bit is set to 1 as soon as an overrun condition is de-

tected by the receiver.

Cleared upon read.

With FIFOs Disabled:

An overrun occurs when a new character is completely

received into the receiver front-end section and the CPU

has not yet read the previous character in the receiver

holding register. The new character is discarded, and

the receiver holding register is not affected.

With FIFOs Enabled:

An overrun occurs when a new character is completely

received into the receiver front-end section and the

RX_FIFO is full. The new character is discarded, and

the RX_FIFO is not affected.

Bit 2 - Parity Error (PE)

This bit is set to 1 if the received data character does not

have the correct parity, even or odd as selected by the

parity control bits of the LCR register.

If the FIFOs are enabled, this error is associated with

the particular character in the FIFO that it applies to.

This error is revealed to the CPU when its associated

character is at the bottom of the RX_FIFO.

This bit is cleared upon read.

Bit 3 - Framing Error (FE)

This bit is set to 1 when the received data character

does not have a valid stop bit (i.e., the stop bit following

the last data bit or parity bit is a 0).

If the FIFOs are enabled, this Framing Error is associat-

ed with the particular character in the FIFO that it ap-

plies to. This error is revealed to the CPU when its

associated character is at the bottom of the RX_FIFO.

After a framing error is detected, the receiver will try to

resynchronize.

If the bit following the erroneous stop bit is 0, the receiv-

er assumes it to be a valid start bit and shifts in the new

character. If that bit is a 1, the receiver enters the idle

state and awaits the next start bit.

This bit is cleared upon read.

Bit 4 - Break Event Detected (BRK)

This bit is set to 1 when a break event is detected (i.e.

when a sequence of logic 0 bits, equal or longer than a

full character transmission, is received). If the FIFOs are

enabled, the break condition is associated with the par-

ticular character in the RX_FIFO to which it applies. In

this case, the BRK bit is set when the character reaches

the bottom of the RX_FIFO.

When a break event occurs, only one zero character is

transferred to the Receiver Holding Register or to the

RX_FIFO.

The next character transfer takes place after at least

one logic 1 bit is received followed by a valid start bit.

This bit is cleared upon read.

Bit 5 - Transmitter Ready (TXRDY)

This bit is set to 1 when the Transmitter Holding Regis-

ter or the TX_FIFO is empty.

It is cleared when a data character is written to the TXD

Bit 6 - Transmitter Empty (TXEMP)

This bit is set to 1 when the Transmitter Holding Regis-

ter or the TX_FIFO is empty, and the transmitter front-

end is idle.

Bit 7 - Error in RX_FIFO (ER_INF)

This bit is set to a 1 if there is at least 1 framing error,

parity error or break indication in the RX_FIFO.

This bit is always 0 in the 16450 mode.

This bit is cleared upon read.

6.5.9

Modem Status Register (MSR)

The function of this register depends on the selected oper-

ational mode. When a UART mode is selected, this register

provides the current-state as well as state-change informa-

tion of the status lines from the modem or data transmission

module.

When loopback is enabled, the MSR register works similar-

ly except that its status input signals are internally driven by

appropriate bits in the MCR register since the modem input

lines are internally disconnected. Refer to at the MCR (see

page 143) and to the LOOP & ETDLBK bits at the EXCR1

(see page 149) for more information.

A description of the various bits of the MSR register, with

Loopback disabled and UART Mode selected, is provided

below.

When bits 0, 1, 2 or 3 is set to 1, a Modem Status Event

(MS_EV) is generated if the MS_IE bit is enabled in the IER

Bits 0 to 3 are set to 0 as a result of any of the following

events:

Hardware reset occurs.

The MSR register is read.

76543210

Reset

Required

Line Status

Bank 0,

BRK

TXRDY

TXEMP

ER_INF

RXDA

Offset 05h

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